AMD-K6-IIIE+550ACR AMD (ADVANCED MICRO DEVICES), AMD-K6-IIIE+550ACR Datasheet - Page 39

• Manufacturer Part Number: AMD-K6-IIIE+550ACR
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AMD-K6-IIIE+550ACR

• Lead Free Status / RoHS Status: Not Compliant

23543A/0—September 2000
Prefetching
Predecode Bits
2.3
Instruction Fetch
Chapter 2
Instruction Fetch and Decode
The AMD-K6-IIIE+ processor conditionally performs cache
prefetching, which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
pipelined cycles.
The 3DNow! technology includes an instruction called
PREFETCH that allows a cache line to be prefetched into the
L1 data cache and the L2 cache. The PREFETCH instruction
format is defined in Table 15, “3DNow!™ Instructions,” on
page 89. For more detailed information, see the 3DNow!™
Technology Manual, order# 21928.
Decoding x86 instructions is particularly difficult because the
instructions are variable-length and can be from 1 to 15 bytes
long. Predecode logic supplies the five predecode bits that are
associated with each instruction byte. The predecode bits
indicate the number of bytes to the start of the next x86
instruction. The predecode bits are stored in an extended
instruction cache alongside each x86 instruction byte as shown
in Figure 2 on page 16. The predecode bits are passed with the
instruction bytes to the decoders where they assist with parallel
x86 instruction decoding.
The processor can fetch up to 16 bytes per clock out of the L1
instruction cache or branch target cache. The fetched
information is placed into a 16-byte instruction buffer that
feeds directly into the decoders (see Figure 3 on page 18).
Fetching can occur along a single execution stream with up to
seven outstanding branches taken.
The instruction fetch logic is capable of retrieving any 16
contiguous bytes of information within a 32-byte boundary.
There is no additional penalty when the 16 bytes of instructions
lie across a cache line boundary. The instruction bytes are
loaded into the instruction buffer as they are consumed by the
decoders.
Although instructions can be consumed with byte granularity,
the instruction buffer is managed on a memory-aligned word
Internal Architecture
AMD-K6™-IIIE+ Embedded Processor Data Sheet
17