AM79C960KCW Advanced Micro Devices, AM79C960KCW Datasheet - Page 77
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AM79C960KCW
Manufacturer Part Number
AM79C960KCW
Description
PCnetTM-ISA Single-Chip Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C960KCW.pdf
(127 pages)
- Current page: 77 of 127
- Download datasheet (815Kb)
Initialization Block
The figure below shows the Initialization Block memory
configuration. Note that the Initialization Block must be
based on a word (16-bit) boundary.
RLEN and TLEN
The TLEN and RLEN fields in the initialization block are
3 bits wide, occupying bits 15,14, and 13, and the value
in these fields determines the number of Transmit and
Receive Descriptor Ring Entries (DRE) which are used
in the descriptor rings. Their meaning is as follows:
IADR+22
IADR+20
IADR+18
IADR+16
IADR+14
IADR+12
IADR+10
IADR+08
IADR+06
IADR+04
IADR+02
IADR+00
Address
TLEN
RLEN
15–12
Bits
RES
RES
RDRA 15–00
LADRF 63–48
LADRF 47–32
LADRF 31–16
LADRF 15–00
PADR 47–32
PADR 31–16
PADR 15–00
MODE 15–00
11–8
Bits
TDRA 15–00
TDRA 23–16
RDRA 23–16
Bits
7–4
P R E L I M I N A R Y
Bits
3–0
Am79C960
If a value other than those listed in the above table is de-
sired, CSR76 and CSR78 can be written after
initialization is complete. See the description of the ap-
propriate CSRs.
RDRA and TDRA
TDRA and RDRA indicate where the transmit and re-
ceive descriptor rings, respectively, begin. Each DRE
must be located on an 8-byte boundary.
LADRF
The Logical Address Filter (LADRF) is a 64-bit mask that
is used to accept incoming Logical Addresses. If the first
bit in the incoming address (as transmitted on the wire)
is a “1”, the address is deemed logical. If the first bit is a
“0”, it is a physical address and is compared against the
physical address that was loaded through the initializa-
tion block.
A logical address is passed through the CRC generator,
producing a 32-bit result. The high order 6 bits of the
CRC are used to select one of the 64 bit positions in the
Logical Address Filter. If the selected filter bit is set, the
address is accepted and the frame is placed into
memory.
R/TLEN
000
001
010
011
100
101
110
111
# of DREs
128
16
32
64
1
2
4
8
AMD
1-419
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