AM79C960KCW Advanced Micro Devices, AM79C960KCW Datasheet - Page 98
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AM79C960KCW
Manufacturer Part Number
AM79C960KCW
Description
PCnetTM-ISA Single-Chip Ethernet Controller
Manufacturer
Advanced Micro Devices
Datasheet
1.AM79C960KCW.pdf
(127 pages)
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SWITCHING CHARACTERISTICS: GPSI
Transmit Timing
Receive Timing
Notes:
1. CLSN must be asserted for a continuous period of 110 ns or more. Assertion for less than 110 ns period may or may
2. RCLK should meet jitter requirements of IEEE 802.3 specification.
3. CLSN assertion before 51.2 s will be indicated as a normal collision. CLSN assertion after 51.2 s will be
Parameter
Symbol
t
t
t
not result in CLSN recognition.
considered as a Late Receive Collision.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
GPR10
GPR11
GPR12
T
AMD
GPR1
GPR2
GPR3
GPR4
GPR5
GPR6
GPR7
GPR8
GPR9
GPT1
GPT2
GPT3
GPT4
GPT5
GPT6
GPT7
GPT8
gpt9
Parameter Description
TCLK Period (802.3 Compliant)
TCLK HIGH Time
TX and TENA Delay from
RENA Setup Before
RENA Hold After
CLSN Active Time to Trigger Collision
CLSN Active to
LCAR Assertion
CLSN Active to
Hearbeat Window
CLSN Active to
RCLK Period
RCLK HIGH Time
RCLK LOW Time
RX and RENA Setup to
RX Hold After
RENA Hold After
CLSN Active to First
(Collision Recognition)
CLSN Active to
Address Type Designation Bit
CLSN Setup to Last
Collision Recognition
CLSN Active
CLSN Inactive Setup to First
CLSN Inactive Hold to Last
RCLK
RENA to Prevent
RENA for SQE
Rena for Normal Collision
RCLK for
TENA
RCLK
TCLK (Last Bit)
RCLK for
RCLK
RCLK
TCLK
RCLK
RCLK
P R E L I M I N A R Y
Am79C960
Test Conditions
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 3)
99.99
51.2
Min
210
110
210
110
300
300
40
80
30
30
15
15
0
0
0
0
0
0
0
100.01
Max
51.2
120
4.0
60
70
80
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
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