PSD913212JIT ST Microelectronics, PSD913212JIT Datasheet - Page 65

• Manufacturer Part Number: PSD913212JIT
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: ST Microelectronics

The
PSD9XX
Functional
Blocks
(cont.)
Preliminary Information
9.6.1 Standard JTAG Signals
The JTAG configuration bit (non-volatile) inside the PSD can be set by the user in the
PSDsoft. Once this bit is set and programmed in the PSD, the JTAG pins are dedicated to
JTAG at all times and is in compliance with IEEE 1149.1. After power up the standard
JTAG signals (TDI, TDO TCK and TMS) are inputs, waiting for a serial command from an
external JTAG controller device (such as FlashLink or Automated Test Equipment). When
the enabling command is received from the external JTAG controller, TDO becomes an
output and the JTAG channel is fully functional inside the PSD. The same command that
enables the JTAG channel may optionally enable the two additional JTAG pins, TSTAT
and TERR.
The PSD9XX supports JTAG In-System-Configuration (ISC) commands, but not
Boundary Scan. ST’s PSDsoft software tool and FlashLink JTAG programming cable
implement these JTAG-ISC commands.
9.6.2 JTAG Extensions
TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received
over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed
programming and erase functions by indicating status on PSD pins instead of
having to scan the status out serially using the standard JTAG channel. See Application
Note 54.
TERR will indicate if an error has occurred when erasing a sector or programming a byte in
Flash memory. This signal will go low (active) when an error condition occurs, and stay
low until a special JTAG command is executed or a chip reset pulse is received after an
“ISC-DISABLE” command.
TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will
be high when the PSD9XX device is in read array mode (Flash memory and Boot Block
contents can be read). TSTAT will be low when Flash memory programming or erase
cycles are in progress, and also when data is being written to the Secondary Flash Block.
TSTAT and TERR can be configured as open-drain type signals with a JTAG command.
9.6.3 Security and Flash Memories Protection
When the security bit is set, the device cannot be read on a device programmer or through
the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed.
All other program/erase/verify commands are blocked. Full chip erase returns the part to a
non-secured blank state. The Security Bit can be set in PSDsoft.
All Flash Memory and Boot sectors can individually be sector protected against erasures.
The sector protect bits can be set in PSDsoft.
PSD9XX Family
61