CDP1805 Intersil Corporation, CDP1805 Datasheet - Page 16

• Manufacturer Part Number: CDP1805
• Description: CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer
• Manufacturer: Intersil Corporation

State Transitions
The CDP1805A and CDP1806A state transitions are shown
in Figure 13. Each machine cycle requires the same period
of time, 8 clock pulses, except the initialization cycle (INlT)
CLOCK
WAIT
TPA
70
FIGURE 12A. TPA PAUSE TIMING
71
t
00
PLH
S1 RESET
DMA
S2 DMA
S1 INIT
t
SU
01
ENTER
PAUSE
PAUSE
t
H
PAUSE
DMA
RESUME
RESET
RUN
DMA FORCE S1
DMA INT
10
FIGURE 12. PAUSE MODE TIMING WAVEFORMS
t
SU
DMA + INT
11
FIGURE 13. STATE TRANSITION DIAGRAM
CDP1805AC, CDP1806AC
20
DMA
“68”
21
t
PHL
30
S1 EXECUTE
PAUSE
SO FETCH
DMA
IDLE DMA
INT DMA
16
which requires 9 clock pulses. Reset is asynchronous and
can be forced at any time.
NOTE:
CLOCK
FORCE S0
9. Pause (in clock waveform) while represented here as one clock
DMA IDLE INT
WAIT
TPB
(LONG BRANCH,
LONG SKIP, NOP, RSXD, ETC)
FORCE S1
cycle in duration, could be infinitely long.
FORCE S0
FORCE S1
INT
DMA
50
INT DMA
FIGURE 12B. TPB PAUSE TIMING
51
t
PLH
S3 INT
t
SU
ENTER
PAUSE
60
RESET
PAUSE
t
INT DMA FORCE S1
H
PAUSE
RESUME
RUN
PRIORITY: RESET
61
t
SU
70
71
FORCE S0, S1
DMA IN
DMA OUT
INT
00
t
PHL
01
10