CDP1805 Intersil Corporation, CDP1805 Datasheet - Page 22

• Manufacturer Part Number: CDP1805
• Description: CMOS 8-Bit Microprocessor with On-Chip RAM and Counter/Timer
• Manufacturer: Intersil Corporation

NOTES:
10. Previous contents of T register are destroyed during instruction execution.
11. This instruction is associated with more than one mnemonic. Each mnemonic is individually listed.
12. ETQ cleared by LDC with the Counter/Timer stopped, reset of CPU, or BCl • (Cl = 1).
13. Cl = Counter Interrupt, Xl = External Interrupt.
14. An IDLE instruction initiates an S1 cycle. All external signals, except the oscillator, are stopped on the low-to-high transition of TPB. All
15. Long-Branch, Long-Skip and No Op instructions require three cycles to complete (1 fetch + 2 execute).
OUTPUT 6
OUTPUT 7
INPUT 1
INPUT 2
INPUT 3
INPUT 4
INPUT 5
INPUT 6
INPUT 7
CALL AND RETURN
STANDARD CALL
STANDARD RETURN
outputs remain in their previous states, MRD, MWR, are set to a logic ‘1’ and the data bus floats. The processor will continue to IDLE
until an I/O request (INTERRUPT, DMA-IN, or DMA-OUT) is activated. When the request is acknowledged, the IDLE cycle is terminated
and the I/O request is serviced, and the normal operation is resumed. (To respond to an lNTERRUPT during an IDLE, MlE and either
ClE or XlE must be enabled).
Long-Branch instructions are three bytes long. The first byte specifies the condition to be tested; and the second and third byte, the
branching address.
The long branch instruction can:
a. Branch unconditionally
b. Test for D = 0 or D
c. Test for DF = 0 or DF = 1
d. Test for Q = 0 or Q = 1
e. Effect an unconditional no branch
If the tested condition is met, then branching takes place; the branching address bytes are loaded in the high-and-low-order bytes of the
current program counter, respectively. This operation effects a branch to any memory location.
If the tested condition is not met, the branching address bytes are skipped over, and the next instruction in sequence is fetched and exe-
cuted. This operation is taken for the case of unconditional no branch (NLBR).
INSTRUCTION
0
TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued)
MACHINE
CYCLES
NO. OF
10
2
2
2
2
2
2
2
2
2
8
CDP1805AC, CDP1806AC
MNEMONIC
OUT 6
OUT 7
SRET
SCAL
INP 1
INP 2
INP 3
INP 4
INP 5
INP 6
INP 7
22
OP CODE
(Note 10)
(Note 10)
689N
688N
6A
6B
6C
6D
6E
66
67
69
6F
M(R(X))
N LINES = 6
M(R(X))
N LINES = 7
BUS
N LINES = 1
BUS
N LINES = 2
BUS
N LINES = 3
BUS
N LINES = 4
BUS
N LINES = 5
BUS
N LINES = 6
BUS
N LINES = 7
R(N).0
R(N).1
R(X) - 2
THEN M(R(N))
M(R(N) + 1)
R(N) + 2
R(N)
M(R(X) + 1)
M(R(X) + 2)
M(R(X)); BUS
M(R(X)); BUS
M(R(X)); BUS
M(R(X)); BUS
M(R(X)); BUS
M(R(X)); BUS
M(R(X)); BUS
R(P);
M(R(X));
M(R(X) - 1);
R(X); R(P)
BUS; R(X) + 1
BUS; R(X) + 1
R(N)
R(N).1;
R(N).0; R(X) + 2
R(P).0;
R(P).1;
OPERATION
D
D
D
D
D
D
D
R(N);
R(X)
R(X)
R(X)