PSD913F1-B-90JI ST Microelectronics, PSD913F1-B-90JI Datasheet - Page 78

• Manufacturer Part Number: PSD913F1-B-90JI
• Description: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
• Manufacturer: ST Microelectronics

PLD Combinatorial Timing
PSD9XX Family
Microcontroller Interface – PSD9XXFV AC/DC Parameters
(3 V Versions)
Write Timing
74
NOTES: 1. Any input used to select an internal PSD813F function.
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
Symbol
t
t
Symbol
PD
ARD
t
t
t
t
t
t
t
t
t
t
t
t
LVLX
AVLX
LXAX
AVWL
SLWL
DVWH
WHDX
WLWH
WHAX1
WHAX2
WHPV
AVPV
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Address hold time for DPLD inputs that are used to generate chip selects for internal PSD memory.
PLD Input Pin/Feedback
to PLD Combinatorial
Output
PLD Array Delay
ALE or AS Pulse Width
Address Setup Time
Address Hold Time
Address Valid to Leading
Edge of WR
CS Valid to Leading Edge of WR
WR Data Setup Time
WR Data Hold Time
WR Pulse Width
Trailing Edge of WR to Address Invalid
Trailing Edge of WR to DPLD Address
Input Invalid
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
Address Input Valid to Address
Output Delay
(3 V Versions)
Parameter
Parameter
(3 V Versions)
Micro Cell
Conditions Min
Any
-12
(Notes 1 and 3)
(Notes 3 and 4)
Conditions
Max
40
25
(Note 1)
(Note 1)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 2)
Min
-15
Max
45
29
Min
26
17
17
45
46
10
9
9
7
0
-12
Min
Max
-20
33
33
Max
50
33
Min
26
10
12
20
20
45
48
12
8
0
-15
Add 4
Add 4
Aloc
Fast
PT
Max
35
35
Preliminary Information
TURBO
Add 20 Sub 6
OFF
Min
30
12
14
25
25
50
10
53
17
0
-20
(Note 1)
Slew
Rate
Max
40
40
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns