UPD6125AG NEC, UPD6125AG Datasheet - Page 8

• Manufacturer Part Number: UPD6125AG
• Description: 4-BIT SINGLE CHIP MICROCONTROLLER FOR REMOTE CONTROL TRANSMISSION
• Manufacturer: NEC

10. TIMER
as the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier output validity.
down count operation. Down counting stops after all of the 9 bits become 0. When down counting is stopped, the
signal indicating that the timer operation has stopped, is output. If the CPU is at standby (HALT TIMER) for the timer
operation completion, the standby (HALT) condition is released and the next instruction will be executed. If the next
instruction again sets the value of the down counter, down counting continues without any error (the carrier output
of the REM pin is not affected).
to the timer is done by the timer manipulation instruction.
or not to output the carrier can be selected by the MSB for the timer register block. Set “1”, when outputting the carrier,
or “0”, when not outputting the carrier.
outputting the carrier, the REM pin output will become low level.
OUT pin is low, when the carrier is being output to the REM pin, or it is high, when the carrier is not being output to
the REM pin.
the oscillation stop mode is initiated after down counting is stopped (after 0).
cleared to 000H.
8
The timer block determines the transmission output pattern. The timer consists of 10 bits, of which 9 bits serve
The 9-bit down counter is decremented (-1) every 8/f
Set the down count time according to the following calculation; (set value (HEX) + 1) x 8/f
When the down counter is operating, the remote control transmission carrier can be output to the REM pin. Whether
If all the down counter bits become “0”, when outputting the carrier, the carrier output will be stopped. When not
A signal in synchronization with the REM output is output to the S-OUT pin. However, the waveform for the S-
If the HALT instruction, which initiates the oscillation stop mode, is executed when the down counter is operating,
Timer operation STOP/RUN is controlled by the control register (P
When “all clear” is input or on reset, the REM pin goes low and S-OUT pin goes high. All 10 bits of the timer are
Caution
S–OUT
REM
Because the timer clock is not synchronized with the carrier output, the pulse width may be
shortened at the beginning and end of the carrier output.
Carrier
(fosc/12, fosc/8)
Selected by control register
Figure 10-1. Timer Block Organization
MSB
1/0
Clear
Set by timer mainpulation instruction
Zero detection circuit
OSC
(s) in synchronization with the machine cycle, after starting
9-bit down counter
1
). (Refer to 13. CONTROL REGISTER (P
D of control register P
2
(Timer RUN/STOP)
OSC
PD6125A, 6126A
. Setting the value
1
fosc / 8
1
).)