UPD63310GK-9EU NEC, UPD63310GK-9EU Datasheet
UPD63310GK-9EU
Related parts for UPD63310GK-9EU
UPD63310GK-9EU Summary of contents
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The PD63310 is an LSI that features two channels each of on-chip 16-bit ADC and DAC circuits for mutual conversion between digital signals and audio signals (having a maximum signal bandwidth of 24 kHz). The analog signal input block enables ...
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BLOCK DIAGRAM Decimeter ADC Mixer MIC AMP + – 2 Digital I/O terminals I/O interface Digital filter Decimeter Interpolator Interpolator Analog loopback (for test mode selection) ADC DAC Mixer Filter MIC AMP Mixer + – Analog I/O ...
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PIN CONFIGURATION (Top View) 80-pin plastic TQFP (FINE PITCH) (12 • PD63310GK-9EU IN1R 1 IN2R 2 IN3R 3 IN4R 4 ...
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... Test mode setting pins. These pins set the test mode when at high level. When not used (i.e., during normal operation mode), connect these pins to GND. Reset signal input pin. A reset occurs when a low pulse (pulse width fs) or greater) is input after starting MCLK ...
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... Analog ground pins. Analog power supply pin. Used for input voltage range +5 connection Reference voltage input pin for R-channel DAC. This pin is usually connected to VRRO pin. Reference voltage output pin for R-channel DAC. Output is 1.4 V (TYP.). Connects to analog GND via a bypass capacitor. ...
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... NC — 6 Function Reference voltage output pin for L-channel ADC. Output is 1.4 V (TYP.). Connects to analog GND via a bypass capacitor. Analog ground pin. No connection Analog ground pins. R-channel mic amp noninverting input pin. If the R-channel mic amp is not being used, connect this pin to VXRO pin. ...
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... OEB is output as the bus driver’s enable signal and RBW is output as the bus driver’s direction specification signal. Use this pin as necessary not used, leave it unconnected. When the clock (data) input to the MCLK and SI pins has been stopped, set these pins to either high level or low level ...
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... Since the ADC’s full scale analog input signal amplitude voltage is 1.4 V (TYP.), it may be necessary to specify a volume setting whereby the signal amplitude’s maximum voltage (after mixing more than 1.4 V, especially when several analog signals are input to the ADC after mixing ...
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Volume Setting Register Data (Command Types) The data in the volume setting registers is written and read based on 6-bit parallel data that is input and output via the DATA5 to DATA0 pins when the SELR pin is set ...
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indicate the data used to control gain in the IN4R register’s input signal, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when ...
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indicate data that controls the gain when outputting the L-channel DAC’s output signal to OUTL, with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = ...
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... Since the mic amp is independent from other blocks, if the mic amp’s output is input to the ADC (or is mixed with output from the DAC), the mic amp’s output pin should be connected via a coupling capacitor to one of the analog signal input pins (see Figure 2-1). ...
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... If this noise is audible enough problem, take the following measures. (1) Set mute mode for the volume (addresses 17 and 18) between the DAC output and the output mixer. (2) Connect the DAC output pins (DACL and DALR) via a capacitor to a pair of unused analog input pins (such as IN4L and IN4R). ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (unless otherwise specified, DGND = AGND = 0 V) Parameter Symbol Power supply voltage V DD Analog input voltage V AIN Digital input voltage V DIN Applied voltage to analog output pin V AOUT ...
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DC Characteristics (unless otherwise specified (1) Power consumption Parameter Symbol Operating current I DD Operating current I DD Standby current I DDstb (2) Digital block Parameter Symbol Input leakage current I LI Output leakage current I ...
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Transmission Characteristics (unless otherwise specified AGND = 0 V, master clock = 12.288 MHz, and on-chip reference voltage power supply is used) (1) AD side Parameter Symbol AD peak S/N SNP X AD dynamic range ...
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AC Characteristics (unless otherwise specified Parameter Symbol RSTB-CSB setup time t RSUC RSTB-SELR setup time t RSUS CSB-WB setup time t CSSUW SELR-WB setup time t SESU SELR-WB hold time t SEHD Time between SELR and ...
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Parallel interface write timing 1 RSTB t RSUC CSB t CSSUW SELR t t RSUS SESU WB DATA5- DATA0 OEB RBW SEHD BSW t STW WDDV WDSU DHDW WDDV PD63310 t CSHD t ...
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Parallel interface write timing 2 (when there are continual write cycles while CSB is low) RSTB t RSUC CSB t CSSUW SELR t t RSUS SESU WB DATA5- DATA0 t OEB RBW t t SEHD BSW t STW t t ...
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Parallel interface read timing 1 RSTB t RSUC CSB t CSSUW SELR t t SESU RSUS WB RB DATA5- DATA0 OEB RBW 20 t SEHD t t STW BSR WDDV WDSU DHDW RDDV PD63310 t CSHDR ...
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Parallel interface read timing 2 (when there are continual read cycles while CSB is low) RSTB t RSUC CSB t CSSUW SELR t t RSUS SESU WB RB DATA5- DATA0 t WDDV OEB RBW t SEHD t t STW BSR ...
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Serial interface input timing BCLK t t DIS DIH SI Serial interface output timing BCLK t DOD SO t BLD LRCLK 22 t BLD PD63310 ...
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APPLICATION CIRCUIT EXAMPLE 4 4 100 R-ch 4 mic input + 1 IN1R + 2 IN2R R-ch + line input 3 IN3R + 4 ...
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... RECOMMENDED LAYOUT PATTERN When laying out the power supply lines and GND lines on the circuit board, refer to the following figure concerning the layout of bypass capacitors. Figure 5-1. Diagram of Recommended Bypass Capacitor Connections (Top View) DIGITAL GND + Remark (4 Tantalum capacitor (0 Chip ceramic capacitor ...
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PACKAGE DRAWING 80 PIN PLASTIC TQFP (FINE PITCH NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition ...
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... VPS Package peak temperature: 215 C, Reflow time: 40 seconds or below (at 200 C or higher), Number of reflow processes: 2 max., Exposure limit Note : 7 days (after that, prebaking is necessary at 125 C for 10 hours) Pin partial heating Pin temperature: 300 C or below, Time: 3 seconds or below (per device side) Note The number of days for storage after the dry pack has been opened ...
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... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...
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... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...