HY27UF161G2A HYNIX [Hynix Semiconductor], HY27UF161G2A Datasheet - Page 14

• Manufacturer Part Number: HY27UF161G2A
• Description: 1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
• Manufacturer: HYNIX [Hynix Semiconductor]

HY27UF(08/16)1G2A Series
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operation is com-
pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the com-
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE,
whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory
connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer
to Table 14 for specific Status Register definitions, and Figure 10 for specific timings requirements . The command reg-
ister remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read dur-
ing a random read cycle, the read command (00h) should be given before starting read cycles.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Four read cycles sequentially output the 1st cycle (ADh), and 2nd cycle (the device code) and
3rd cycle ID, 4th cycle ID, respectively. The command register remains in Read ID mode until further commands are
issued to it. Figure 19 shows the operation sequence, while Tables 16 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased.
The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when
WP is high. Refer to table 14 for device status after reset operation. If the device is already in reset state a new reset
command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset com-
mand is written.
Rev 0.4 / Jun. 2007
14