HY27US08121B HYNIX [Hynix Semiconductor], HY27US08121B Datasheet

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HY27US08121B

Manufacturer Part Number
HY27US08121B
Description
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Manufacturer
HYNIX [Hynix Semiconductor]
Datasheet

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DESCRIPTION
Hynix HYMD232646B(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules(DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD232646B(L)8-M/
K/H/L series consists of eight 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy sub-
strate.Hynix HYMD232646B(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor
of industry standard. It is suitable for easy interchange and addition.
Hynix HYMD232646B(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD232646B(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
ORDERING INFORMATION
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2/Dec. 02
HYMD232646B(L)8-M
HYMD232646B(L)8-K
HYMD232646B(L)8-H
HYMD232646B(L)8-L
256MB (32M x 64) Unbuffered DDR DIMM based on
32Mx8 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Data(DQ), Data strobes and Write masks latched on
both rising and falling edges of the clock
Part No.
Power Supply
V
V
DDQ
DD
=2.5V
=2.5V
133MHz (*DDR266:2-2-2)
133MHz (*DDR266A)
133MHz (*DDR266B)
100MHz (*DDR200)
Clock Frequency
Unbuffered DDR SDRAM DIMM
Data inputs on DQS centers when write (centered
DQ)
Data strobes synchronized with output data for read
and input data for write
Programmable CAS Latency 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
tRAS Lock-out function supported
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
HYMD232646B(L)8-M/K/H/L
Interface
SSTL_2
* JEDEC Defined Specifications compliant
184pin Unbuffered DIMM
5.25 x 1.25 x 0.15 inch
Form Factor
32Mx64 bits
1

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HY27US08121B Summary of contents

Page 1

DESCRIPTION Hynix HYMD232646B(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 32Mx64 high-speed memory arrays. Hynix HYMD232646B(L)8-M/ K/H/L series consists of eight 32Mx8 DDR SDRAM in 400mil TSOP II packages on ...

Page 2

PIN DESCRIPTION Pin Pin Description CK0,/CK0,CK1,/CK1,CK2,/CK2 Differential Clock Inputs CS0 Chip Select Input CKE0 Clock Enable Input /RAS, /CAS, /WE Commend Sets Inputs A0 ~ A12 Address BA0, BA1 Bank Address DQ0~DQ63 Data Inputs/Outputs DQS0~DQS7 Data Strobe Inputs/Outputs DM0~DM7 Data-in ...

Page 3

FUNCTIONAL BLOCK DIAGRAM /CS0 /CS0 DQS0 DQS0 DM0 DM0 DM DM DQ0 DQ0 I/O 7 I/O 7 DQ1 DQ1 I/O 6 I/O 6 DQ2 DQ2 I/O 1 I/O 1 DQ3 DQ3 I/O 0 I/O 0 DQ4 DQ4 I/O 5 I/O ...

Page 4

ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Voltage on V relative to V DDQ SS Output Short Circuit Current Power Dissipation Soldering Temperature ...

Page 5

AC OPERATING TEST CONDITIONS Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (V , min Input Low Level Voltage (V , max) IL Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input ...

Page 6

CAPACITANCE o (T =25 C, f=100MHz ) A Parameter Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Input Capacitance Data Input / Output Capacitance Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC ...

Page 7

DC CHARACTERISTICS I Parameter Add, CMD, /CS, /CKE Input Leakage Current CK, /CK Output Leakage Current Output High Voltage Output Low Voltage Note : 3.6V, All other pins are not tested under ...

Page 8

DC CHARACTERISTICS II Parameter Symbol One bank; Active Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs Operating Current IDD0 changing twice per clock cycle; address and control inputs changing once per clock cycle One bank; Active - Read Precharge; Burst Length ...

Page 9

AC CHARACTERISTICS Parameter Symbol Row Cycle Time Auto Refresh Row Cycle Time t Row Active Time t Active to Read with Auto t Precharge Delay Row Address to Column t Address Delay Row Active to Row Active Delay t Column ...

Page 10

AC CHARACTERISTICS Parameter Symbol Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width t Write DQS Low ...

Page 11

CK, /CK slew rates are >=1.0V/ns 6. These parameters quarantee device timing, but they are not necessarily tested on each device, and they may be quaranteed by design or tester correlation. 7. Data latched at both rising and falling ...

Page 12

SIMPLIFIED COMMAND TRUTH TABLE Command CKEn-1 Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self ...

Page 13

PACKAGE DIMENSIONS (2) 0 2.5 0.098 Rev. 0.2/Dec. 02 Front 133.35 5.25 131.35 5.171 128.95 5.077 HYMD232646B(L)8-M/K/H/L 0.125MAX (Front) 31.75 1.250 1.27+/-0.10 0.050+/-.004 Side 3.18 13 ...

Page 14

SPD SPECIFICATION (32Mx64 Unbuffered DDR DIMM) Rev. 0.3/Jul. 02 SERIAL PRESENCE DETECT 14 ...

Page 15

SERIAL PRESENCE DETECT Byte# Function Description Number of Bytes written into serial memory at module 0 manufacturer 1 Total number of Bytes in SPD device 2 Fundamental memory type 3 Number of row address on this assembly 4 Number of ...

Page 16

SERIAL PRESENCE DETECT Byte # Function Description 64 Manufacturer JEDEC ID Code 65~71 --------- Manufacturer JEDEC ID Code 72 Manufacturing location 73 Manufacture part number(Hynix Memory Module) 74 -------- Manufacture part number(Hynix Memory Module) 75 -------- Manufacture part number(Hynix Memory ...

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