AM29F032B-120 AMD [Advanced Micro Devices], AM29F032B-120 Datasheet - Page 10

• Manufacturer Part Number: AM29F032B-120
• Description: 32 Megabit (4 M x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
read specifications apply. Refer to “The Erase Resume
command is valid only during the Erase Suspend
mode.” for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when CE#
and RESET# pins are both held at V
that this is a more restricted voltage range than V
The device enters the TTL standby mode when CE#
and RESET# pins are both held at V
quires standard access time (t
the device is in either of these standby modes, before it
is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is driven low. Refer to the next section, “RE-
SET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, I
standby current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
CE
) for read access when
CC3
IH
CC
. The device re-
represents the
± 0.5 V. (Note
Am29F032B
IH
CC
.)
drives the RESET# pin low for at least a period of t
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
the TTL standby mode; if RESET# is held at V
0.5 V, the device enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the in-
ternal reset operation is complete, which requires a
time of t
tem can thus monitor RY/BY# to determine whether the
reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
SET# pin returns to V
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high imped-
ance state.
READY
(during Embedded Algorithms). The sys-
READY
IH
.
(not during Embedded Algo-
IH
, output from the device is
IL
, the device enters
RH
after the RE-
SS
RP
9
±
,