EVAL-AD7843CB3 AD [Analog Devices], EVAL-AD7843CB3 Datasheet - Page 12

• Manufacturer Part Number: EVAL-AD7843CB3
• Description: Touch Screen Digitizer
• Manufacturer: AD [Analog Devices]

AD7843
PD1
0
0
1
1
POWER VS. THROUGHPUT RATE
By using the power-down options on the AD7843 when not con-
verting, the average power consumption of the device decreases at
lower throughput rates. Figure 8 shows how, as the through-
put rate is reduced while maintaining the DCLK frequency at
2 MHz, the device remains in its power-down state longer and
the average current consumption over time drops accordingly.
For example, if the AD7843 is operated in a 24 DCLK continu-
ous sampling mode, with a throughput rate of 10 kSPS and a
SCLK of 2 MHz, and the device is placed in the power-down
mode between conversions, (PD0, PD1 = 0, 0), the current
consumption is calculated as follows. The power dissipation
during normal operation is typically 210 µA (V
power-up time of the ADC is instantaneous, so when the part
is converting it will consume 210 µA. In this mode of operation
the part powers up on the 4th falling edge of DCLK after the
start bit has been recognized. It goes back into power-down at
the end of conversion on the 20th falling edge of DCLK. This
means the part will consume 210 µA for 16 DCLK cycles only,
8 µs, during each conversion cycle. With a throughput rate of
10 kSPS, the cycle time is 100 µs and the average power dissi-
pated during each cycle is (8/100) × (210 µA) = 16.8 µA.
1000
100
10
PD0
1
0
0
1
0
1
f
f
DCLK
DCLK
20
= 16 f
= 2MHz
PENIRQ
Enabled
Disabled
Enabled
Disabled
40
SAMPLE
THROUGHPUT – kSPS
60
Description
This configuration will result in power-down of the device between conversions. The AD7843
will only power down between conversions. Once PD1 and PD0 have been set to 0, 0, the
conversion will be performed first and the AD7843 will power down upon completion of that
conversion. At the start of the next conversion, the ADC instantly powers up to full power. This
means there is no need for additional delays to ensure full operation and the very first conversion
is valid. The Y– switch is ON while in power-down.
This configuration will result in the same behavior as when PD1 and PD0 have been programmed
with 0, 0, except that PENIRQ is disabled. The Y– switch is OFF while in power-down.
This configuration will result in keeping the AD7843 permanently powered up with the PENIRQ
enabled.
This configuration will result in keeping the AD7843 always powered up with the PENIRQ
disabled.
80
V
T
A
CC
= –40 C to +85 C
= 2.7V
100
Table III. Power Management Options
CC
= 2.7 V). The
120
µ
SERIAL INTERFACE
Figure 9 shows the typical operation of the serial interface of the
AD7843. The serial clock provides the conversion clock and
also controls the transfer of information to and from the AD7843.
One complete conversion can be achieved with twenty-four
DCLK cycles.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS takes the BUSY output and the serial
bus out of three-state. The first eight DCLK cycles are used to
write to the Control Register via the DIN pin. The Control
Register is updated in stages as each bit is clocked in and once
the converter has enough information about the following con-
version to set the input multiplexer and switches appropriately,
the converter enters the acquisition mode and if required, the
internal switches are turned on. During the acquisition mode
the reference input data is updated. After the three DCLK
cycles of acquisition, the control word is complete (the power
management bits are now updated) and the converter enters the
conversion mode. At this point the track and hold goes into hold
mode and the input signal is sampled and the BUSY output
goes high (BUSY will return low on the next falling edge of
DCLK). The internal switches may also turn off at this point if
in single-ended mode.
The next 12 DCLK cycles are used to perform the conversion
and to clock out the conversion result. If the conversion is
ratiometric (SER/DFR set low) the internal switches are on
during the conversion. A thirteenth DCLK cycle is needed to
allow the DSP/micro to clock in the LSB. Three more DCLK
cycles will clock out the three trailing zeroes and complete the
twenty four DCLK transfer. The twenty-four DCLK cycles may
be provided from a DSP or via three bursts of eight clock cycles
from a microcontroller.