EVAL-ADAU1702EB AD [Analog Devices], EVAL-ADAU1702EB Datasheet - Page 27

• Manufacturer Part Number: EVAL-ADAU1702EB
• Description: SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs
• Manufacturer: AD [Analog Devices]

The writeback function writes data from the ADAU1702
interface registers to the second page of the self-boot EEPROM,
Address 32 to Address 63. Starting at EEPROM Address 26
(so that the interface register data begins at Address 32), the
EEPROM should be programmed with six bytes—the message
byte (0x01), two length bytes, the chip address (0x00), and the
2-byte subaddress for the interface registers (0x08, 0x00). There
must be a message to the DSP core control register to enable
writing to the interface registers prior to the interface register
data in the EEPROM. This should be stored in EEPROM
Address 0. No-op messages (0x03) can be used in between
messages to ensure that these conditions are met.
Table 19. EEPROM Message Types
Message ID
0x00
0x01
0x02
0x03
0x04
0x05
0x06
Table 20. EEPROM Data Example
10
11
1
2
3
4
5
6
7
8
9
Write
Write
0x01
0x03
0x03
0x03
0x00
0x00
0x00
0x00
0x01
0x00
0x00
No-op bytes
0x00
0x03
0x03
0x03
0x00
0x00
0x00
0x00
0x01
0x00
0x00
Length
Length
Message Type
End
Write
Delay
No operation executed
Set multiple writeback
Set WB to falling edge sensitive
End and wait for writeback
0x05
0x03
0x03
0x01
Write
0x00
0x00
0x00
0x00
0x61
0x01
0x00
Program RAM data (continues for 332 more bytes)
Device addr.
Device addr.
0x00
0x03
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
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Interface register data
Interface register data
Interface register data
Interface register data
Program RAM data
No-op bytes
No-op bytes
Length
Core control register address
The ADAU1702 writes to EEPROM Chip Address 0xA0. The
LSBs of the addresses of some EEPROMs are pin configurable; in
most cases, these pins should be tied low to set the address to 0xA0.
The maximum number of bytes that is written back from the
ADAU1702 is 35 (eight 4-byte interface registers plus three
bytes of EEPROM-addressing overhead). With SCL running at
384 kHz, the writeback operation takes approximately 73 μs to
complete after being triggered. Ensure that sufficient power is
available to the system to allow enough time for a writeback to
complete, especially if the WB signal is triggered from a falling
power supply voltage.
Following Bytes
None
Two bytes indicating message length followed by appropriate
number of data bytes
Two bytes for delay
None
None
None
None
0x08
0x03
0x03
0x23
0x00
0x00
0x00
0x00
0x04
0x00
0x01
Program RAM address
Device addr.
0x1C
0x03
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Core control register data
Interface register address
0x00
0x03
0x03
0x08
0x00
0x00
0x00
0x00
0x00
0xE8
0x08
Program RAM data
ADAU1702
0x40
0x03
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x00