EVAL-ADAU1702EB AD [Analog Devices], EVAL-ADAU1702EB Datasheet - Page 39

• Manufacturer Part Number: EVAL-ADAU1702EB
• Description: SigmaDSP 28-56-Bit Audio Processor with Two ADCs and Four DACs
• Manufacturer: AD [Analog Devices]

2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER
Table 48.
D15
0
Table 49.
Bit Name
OLRP
OBP
M/S
OBF [1:0]
OLF [1:0]
FST
TDM
MSB [2:0]
OWL [1:0]
OUTPUT_LRCLK Polarity
OUTPUT_BCLK Polarity
Master/Slave
OUTPUT_BCLK Freq
(Master Mode Only)
OUTPUT_LRCLK Freq
(Master Mode Only)
Frame Sync Type
TDM Enable
MSB Position
Output Word Length
D14
0
D13
OLRP
D12
OBP
Description
When this bit is set to 0, the left-channel data is clocked when OUTPUT_LRCLK is low and the right-channel
data is clocked when OUTPUT_LRCLK is high. When this bit is set to 1, the right-channel data is clocked when
OUTPUT_LRCLK is low and the left-channel data is clocked when OUTPUT_LRCLK is high.
This bit controls on which edge of the bit clock the output data is clocked. Data changes on the falling edge
of OUTPUT_BCLK when this bit is set to 0 and on the rising edge when this bit is set to 1.
This bit sets whether the output port is a clock master or slave. The default setting is slave; on power-up, the
OUTPUT_BCLK and OUTPUT_LRCLK pins are set as inputs until this bit is set to 1, at which time they become
clock outputs.
When the output port is being used as a clock master, these bits set the frequency of the output bit clock,
which is divided down from an internal 1024 × f
OBF [1:0]
00
01
10
11
When the output port is used as a clock master, these bits set the frequency of the output word clock on the
OUTPUT_LRCLK pins, which is divided down from an internal 1024 × f
OLF [1:0]
00
01
10
11
This bit sets the type of signal on the OUTPUT_LRCLK pins. When this bit is set to 0, the signal is a word clock
with a 50% duty cycle; when this bit is set to 1, the signal is a pulse with a duration of one bit clock at the
beginning of the data frame.
Setting this bit to 1 changes the output port from four serial stereo outputs to a single 8-channel TDM output
stream on the SDATA_OUT0 pin (MP6).
These three bits set the position of the MSB of data with respect to the LRCLK edge. The data output of the
ADAU1702 is always MSB first.
MSB [2:0]
000
001
010
011
100
101
111
These bits set the word length of the output data-word. All bits following the LSB are set to 0.
OWL [1:0]
00
01
10
11
D11
M/S
D10
OBF1
Setting
Internal clock/16
Internal clock/8
Internal clock/4
Internal clock/2
Setting
Internal clock/1024
Internal clock/512
Internal clock/256
Reserved
Setting
Delay by 1
Delay by 0
Delay by 8
Delay by 12
Delay by 16
Reserved
Reserved
Setting
24 bits
20 bits
16 bits
Reserved
D9
OBF0
D8
OLF1
Rev. 0 | Page 39 of 52
D7
OLF0
D6
FST
S
D5
TDM
clock (49.152 MHz for a f
D4
MSB2
D3
MSB1
S
clock (49.152 MHz for a f
S
D2
MSB0
of 48 kHz).
D1
OWL1
S
of 48 kHz).
D0
OWL0
ADAU1702
Default
0x0000