EVAL-ADN2805EBZ AD [Analog Devices], EVAL-ADN2805EBZ Datasheet

no-image

EVAL-ADN2805EBZ

Manufacturer Part Number
EVAL-ADN2805EBZ
Description
1.25 Gbps Clock and Data Recovery IC
Manufacturer
AD [Analog Devices]
Datasheet
FEATURES
Locks to 1.25 Gbps NRZ serial data input
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
I
Single-supply operation: 3.3 V
Low power: 390 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb free
APPLICATIONS
GbE line card
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2
C interface to access optional features
VREF
NIN
PIN
BUFFER
REFCLKP/REFCLKN
FUNCTIONAL BLOCK DIAGRAM
(OPTIONAL)
1.25 Gbps Clock and Data Recovery IC
DATAOUTP/
DATAOUTN
RE-TIMING
SHIFTER
PHASE
DATA
2
Figure 1.
LOL
FREQUENCY
DETECT
CLKOUTP/
DETECT
CLKOUTN
PHASE
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2
GENERAL DESCRIPTION
The ADN2805 provides the receiver functions of quantization
and clock and data recovery for 1.25 Gbps. The ADN2805
automatically locks to all data rates without the need for an
external reference clock or programming. All SONET jitter
requirements are met, including jitter transfer, jitter generation,
and jitter tolerance.
All specifications are specified for −40°C to +85°C ambient
temperature, unless otherwise noted. The ADN2805 is available
in a compact 5 mm × 5 mm 32-lead LFCSP.
CF1
FILTER
FILTER
LOOP
LOOP
CF2
ADN2805
VCC
VCO
VEE
©2008 Analog Devices, Inc. All rights reserved.
ADN2805
www.analog.com

Related parts for EVAL-ADN2805EBZ

EVAL-ADN2805EBZ Summary of contents

Page 1

FEATURES Locks to 1.25 Gbps NRZ serial data input Patented clock recovery architecture No reference clock required Loss-of-lock indicator interface to access optional features Single-supply operation: 3.3 V Low power: 390 mW typical 5 mm × 5 ...

Page 2

ADN2805 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Jitter Specifications ....................................................................... 3 Output and Timing Specifications ............................................. 4 Absolute Maximum Ratings ............................................................ ...

Page 3

SPECIFICATIONS VCC = VEE = MIN MAX MIN MAX unless otherwise noted. Table 1. Parameter QUANTIZER—DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level ...

Page 4

ADN2805 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter LVDS OUTPUT CHARACTERISTICS CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN Differential Output Swing Output Offset Voltage Output Impedance LVDS Outputs Timing Rise Time Fall Time Setup Time Hold Time 2 I C® INTERFACE DC CHARACTERISTICS Input High ...

Page 5

Timing Characteristics CLKOUTP DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP Figure 3. Differential Output Specifications 5mA R LOAD 100Ω 100Ω 5mA SIMPLIFIED LVDS OUTPUT STAGE Figure 4. ...

Page 6

ADN2805 ABSOLUTE MAXIMUM RATINGS VCC = MIN MAX MIN MAX 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All ...

Page 7

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 6. Pin Function Descriptions Pin No. Mnemonic 1 TEST1 2 VCC 3 VREF 4 NIN 5 PIN VEE 10 REFCLKP 11 REFCLKN 12 VCC 13 VEE 14 CF2 ...

Page 8

ADN2805 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT SLAVE ADDRESS SDA A6 ...

Page 9

Table 7. Internal Register Map Reg. Name R/W Address D7 FREQ0 R 0x0 MSB FREQ1 R 0x1 MSB FREQ2 R 0x2 0 RATE R 0x3 COARSE_RD[8] MSB MISC R 0x4 X CTRLA W 0x8 f REF CTRLB W ...

Page 10

ADN2805 THEORY OF OPERATION The ADN2805 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that ...

Page 11

The gain of the loop integrator is small for high jitter frequencies; therefore, larger phase differences are needed to make the loop control voltage large enough to tune the range of the phase shifter. Large phase errors at high jitter ...

Page 12

ADN2805 FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION The ADN2805 acquires frequency from the data at 1.25 Gbps. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming data. When these frequen- cies differ by more than ...

Page 13

SQUELCH MODE Two squelch modes are available with the ADN2805. The SQUELCH DATAOUT and CLKOUT mode is selected when CTRLC[ (default mode). In this mode, when the SQUELCH input, Pin 27, is driven to a TTL high state, ...

Page 14

ADN2805 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. To reduce series inductance, solder the VEE pins ...

Page 15

Transmission Lines Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also REFCLKP and REFCLKN high frequency reference clock is used, ...

Page 16

... ADN2805ACPZ −40°C to +85°C 1 ADN2805ACPZ-500RL7 −40°C to +85°C 1 ADN2805ACPZ-RL7 −40°C to +85°C EVAL-ADN2805EBZ RoHS Compliant Part. 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © ...

Related keywords