EVAL-ADN2805EBZ AD [Analog Devices], EVAL-ADN2805EBZ Datasheet - Page 9

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EVAL-ADN2805EBZ

Manufacturer Part Number
EVAL-ADN2805EBZ
Description
1.25 Gbps Clock and Data Recovery IC
Manufacturer
AD [Analog Devices]
Datasheet
Table 7. Internal Register Map
Reg. Name
FREQ0
FREQ1
FREQ2
RATE
MISC
CTRLA
CTRLB
CTRLC
1
2
Table 8. Miscellaneous Register, MISC
D7
X
1
Table 9. Control Register, CTRLA
D7
0
0
1
1
1
Table 10. Control Register, CTRLB
Configure LOL
D7
0 = LOL pin normal operation
1 = LOL pin is static LOL
Table 11. Control Register, CTRLC
D7
Set to 0
All writeable registers default to 0x00.
X = don’t care.
X = don’t care.
Where DIV_f
D6
X
D6
0
1
0
1
REF
D6
Set to 0
D5
X
f
is the divided down reference referred to the 10 MHz to 20 MHz band.
10 MHz to 20 MHz
20 MHz to 40 MHz
40 MHz to 80 MHz
80 MHz to 160 MHz
REF
R/W
R
R
R
R
R
W
W
W
Range
Static LOL
D4
0 = waiting for next LOL
1 = static LOL until reset
Address
0x0
0x1
0x2
0x3
0x4
0x8
0x9
0x11
D5
Set to 0
Reset MISC[4]
D6
Write a 1 followed by
0 to reset MISC[4]
1, 2
D7
MSB
MSB
0
X
Config
LOL
0
D4
Set to 0
1
f
COARSE_RD[8] MSB
REF
D5
0
0
1
0
1
Range
Data Rate/DIV_f
D6
MSB
X
Reset
MISC[4]
0
D4
0
0
0
0
D3
Set to 0
LOL Status
D3
0 = locked
1 = acquiring
n
D3
0
0
1
0
D5
X
System
Reset
0
System Reset
D5
Write a 1 followed by
0 to reset ADN2805
D2
Set to 0
REF
D2
0
1
0
0
Rev. 0 | Page 9 of 16
Ratio
Data Rate/DIV_f
Data Rate Measurement Complete
D2
1 = measurement complete
0 = measuring data rate
D4
Static
LOL
0
0
1
2
4
2
256
Coarse Data Rate Readback
n
Squelch Mode
D1
0 = SQUELCH DATAOUT and CLKOUT
1 = SQUELCH DATAOUT or CLKOUT
Measure Data Rate
D1
Set to 1 to measure data rate
D3
LOL
Status
Reset
MISC[2]
0
D4
Set to 0
REF
Ratio
D2
Data Rate
Measure
Complete
0
0
Reset MISC[2]
D3
Write a 1 followed by
0 to reset MISC[2]
D1
X
Measure Data Rate
0
Squelch Mode
D1
X
Lock to Reference
D0
0 = lock to input data
1 = lock to reference clock
Coarse Rate Readback LSB
D0
COARSE_RD[0]
COARSE_RD[1]
D2
Set to 0
Output Boost
D0
0 = default output swing
1 = boost output swing
D0
LSB
LSB
LSB
COARSE_RD[0]
(LSB)
Lock to Reference
0
Output Boost
D1
Set to 0
ADN2805
D0
Set to 0

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