IDT74ALVCH16260PAG8 IDT, Integrated Device Technology Inc, IDT74ALVCH16260PAG8 Datasheet

IDT74ALVCH16260PAG8

Manufacturer Part Number

IDT74ALVCH16260PAG8

Description

IC LATCH 12-24BIT MUX D 56-TSSOP

Manufacturer

IDT, Integrated Device Technology Inc

Series

74ALVCHr

Type

D-Typer

Datasheet

1.IDT74ALVCH16260PAG8.pdf (7 pages)

Specifications of IDT74ALVCH16260PAG8

Logic Type

D-Type Transparent Latch

Circuit

12:24

Output Type

Tri-State

Voltage - Supply

2.3 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1ns

Current - Output High, Low

24mA, 24mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

56-TSSOP

Logic Family

ALVC

Number Of Bits

Number Of Elements

Latch Mode

Multiplexed

Polarity

Non-Inverting

Technology

CMOS

Package Type

TSSOP

Propagation Delay Time

6.9ns

Operating Supply Voltage (typ)

3.3V

High Level Output Current

-24mA

Low Level Output Current

24mA

Operating Supply Voltage (min)

2.7V

Operating Supply Voltage (max)

3.6V

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

74ALVCH16260PAG8
800-1555-2

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FEATURES:

• 0.5 MICRON CMOS Technology

• Typical t

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

• V

• CMOS power levels (0.4μ μ μ μ μ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• Available in TSSOP package

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Suitable for heavy loads

APPLICATIONS:

• 3.3V high speed systems

• 3.3V and lower voltage computing systems

FUNCTIONAL BLOCK DIAGRAM

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16260

3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH

machine model (C = 200pF, R = 0)

= 3.3V ± 0.3V, Normal Range

= 2.7V to 3.6V, Extended Range

= 2.5V ± 0.2V

SK(o)

(Output Skew) < 250ps

LEA1B

LEA2B

OE1B

OE2B

LE2B

LE1B

OEA

SEL

1:12

3.3V CMOS 12-BIT TO 24-BIT

MULTIPLEXED D-TYPE LATCH

WITH 3-STATE OUTPUTS

AND BUS-HOLD

DESCRIPTION:

metal CMOS technology. The ALVCH16260 is used in applications in which

two separate data paths must be multiplexed onto, or demultiplexed from, a

single data path. Typical applications include multiplexing and/or demultiplexing

address and data information in microprocessor or bus-interface applications.

This device also is useful in memory interleaving applications.

for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA)

inputs control the bus transceiver functions. The OE1B and OE2B control

signals also allow bank control in the A-to-B direction. Address and/or data

information can be stored using the internal storage latches. The latch-enable

(LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage.

When the latch-enable input is high, the latch is transparent. When the latch-

enable input goes low, the data present at the inputs is latched and remains

latched until the latch-enable input is returned high.

driver is capable of driving a moderate to heavy load while maintaining speed

performance.

whenever the input goes to a high impedance. This prevents floating inputs

and eliminates the need for pull-up/down resistors.

LATCH

This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual

Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available

The ALVCH16260 has been designed with a ±24mA output driver. This

The ALVCH16260 has “bus-hold” which retains the inputs’ last state

LATCH

A-1B

2B-A

A-2B

1B-A

INDUSTRIAL TEMPERATURE RANGE

IDT74ALVCH16260

1:12

JULY 2009

DSC-4737/6

Related parts for IDT74ALVCH16260PAG8

IDT74ALVCH16260PAG8 Summary of contents

Page 1

IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH FEATURES: • 0.5 MICRON CMOS Technology • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R ...

Page 2

IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH PIN CONFIGURATION 1 OEA 2 LE1B GND ...

Page 3

IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH FUNCTION TABLES (CONTINUED) A-TO-B (OEA = H) Inputs OE1B OE2B Ax LEA1B LEA2B ...

Page 4

IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW ...

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IDT74ALVCH16260PAG8 IDT, Integrated Device Technology Inc, IDT74ALVCH16260PAG8 Datasheet

IDT74ALVCH16260PAG8

Specifications of IDT74ALVCH16260PAG8

Related parts for IDT74ALVCH16260PAG8

IDT74ALVCH16260PAG8 Summary of contents

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Page 2

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Page 4

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Page 7

Related keywords