74ABT373AN,112 NXP Semiconductors, 74ABT373AN,112 Datasheet - Page 2
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74ABT373AN,112
Manufacturer Part Number
74ABT373AN,112
Description
IC OCTAL TRANSP LATCH 3ST 20DIP
Manufacturer
NXP Semiconductors
Series
74ABTr
Datasheet
1.74ABT373AD118.pdf
(11 pages)
Specifications of 74ABT373AN,112
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
3.6ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74ABT373AN
74ABT373AN
935191320112
74ABT373AN
935191320112
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN CONFIGURATION
20-Pin Plastic DIP
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
1995 Feb 17
8-bit transparent latch
3-State output buffers
Output capability: +64mA/–32mA
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
Power-up 3-State
Power-up reset
Live insertion/extraction permitted
Octal transparent latch (3-State)
SYMBOL
C
I
t
t
C
PLH
PHL
CCZ
OUT
IN
PACKAGES
GND
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
Q0
Q1
OE
D0
D1
Q2
D2
D3
Q3
10
1
2
3
4
5
6
7
8
9
PARAMETER
TEMPERATURE RANGE
20
19
18
17
16
15
14
13
12
11
V
Q7
D7
D6
Q6
Q5
D5
D4
Q4
E
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
–40 C to +85 C
CC
SA00059
C
V
Outputs disabled; V
Outputs disabled; V
L
I
= 0V or V
= 50pF; V
OUTSIDE NORTH AMERICA
2
74ABT373A PW
74ABT373A DB
T
DESCRIPTION
The 74ABT373A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT373A device is an octal transparent latch coupled to
eight 3-State output buffers. The two sections of the device are
controlled independently by Enable (E) and Output Enable (OE)
control gates.
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation.
When OE is Low, the latched or transparent data appears at the
outputs. When OE is High, the outputs are in the High-impedance
“OFF” state, which means they will neither drive nor load the bus.
PIN DESCRIPTION
74ABT373A N
74ABT373A D
CC
amb
CC
PIN NUMBER
3, 4, 7, 8, 13,
2, 5, 6, 9, 12,
14, 17, 18
15, 16, 19
CONDITIONS
= 5V
= 25 C; GND = 0V
11
10
20
O
CC
1
= 0V or V
=5.5V
SYMBOL
CC
Q0-Q7
D0-D7
GND
V
OE
E
CC
NORTH AMERICA
7ABT373APW DH
74ABTD373A B
74ABT373A N
74ABT373A D
Output enable input (active-Low)
Data inputs
Data outputs
Enable input (active-High)
Ground (0V)
Positive supply voltage
TYPICAL
74ABT373A
FUNCTION
100
3.2
3.6
4
7
Product specification
DWG NUMBER
853-1454 14852
SOT146-1
SOT163-1
SOT339-1
SOT360-1
UNIT
pF
pF
ns
A