74ALVCH16841DGG,11 NXP Semiconductors, 74ALVCH16841DGG,11 Datasheet - Page 7
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74ALVCH16841DGG,11
Manufacturer Part Number
74ALVCH16841DGG,11
Description
IC 20BIT BUS INTRFC D 56TSSOP
Manufacturer
NXP Semiconductors
Series
74ALVCHr
Type
D-Typer
Datasheet
1.74ALVCH16841DGG11.pdf
(10 pages)
Specifications of 74ALVCH16841DGG,11
Logic Type
D-Type Transparent Latch
Package / Case
56-TSSOP
Circuit
10:10
Output Type
Tri-State
Voltage - Supply
2.3 V ~ 3.6 V
Independent Circuits
2
Delay Time - Propagation
2.5ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Number Of Circuits
2
Logic Family
ALVC
Polarity
Non-Inverting
Input Bias Current (max)
0.2 uA
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
2.4 ns at 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Number Of Bits
20
Number Of Elements
2
Latch Mode
Transparent
Technology
CMOS
Package Type
TSSOP
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (min)
2.3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
56
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74ALVCH16841DG-T
74ALVCH16841DG-T
935259090118
74ALVCH16841DG-T
935259090118
Philips Semiconductors
AC WAVEFORMS FOR V
V
V
V
V
V
output load.
AC WAVEFORMS FOR V
V
V
V
V
V
output load.
V
V
1998 Jul 27
Waveform 2. The latch enable (LE) pulse width, the latch enable
Waveform 3. The data set up and hold times for the D
I
I
M
X
Y
OL
M
X
Y
OL
CC
CC
Q
OUTPUT
Waveform 1. The input (D
Dn
INPUT
= 2.7V
= V
LE
INPUT
NOTE: The shaded areas indicate when the input is permitted to change
20-bit bus interface D-type latch (3-State)
= V
= V
= V
= V
D
INPUT
n
Qn OUTPUT
= 0.5 V
= 1.5 V
GND
GND
n
and V
and V
GND
V
LE INPUT
< 2.3V RANGE
= 2.7V RANGE
CC
V
V
V
OH
OL
OH
OL
OH
V
OL
É É É
É É É
É É É
I
I
I
for predictable output performance.
GND
+ 0.15V
+ 0.3V
V
–0.15V
–0.3V
V
OH
OH
CC
OH
OL
V
I
input to output (Q
are the typical output voltage drop that occur with the
are the typical output voltage drop that occur with the
V
M
t
V
SU
M
t
PHL
V
t
PHL
É É É É É É É
É É É É É É É
É É É É É É É
M
th
t
V
W
the LE input
M
n
V
) to output (Q
M
V
CC
CC
n
M
) propagation delay
= 2.3V TO 2.7V AND
= 3.0V TO 3.6V AND
t
PLH
V
n
M
) propagation delay
t
SU
t
PLH
É É É
É É É
É É É
SH00150
th
SH00153
n
SH00149
input to
7
TEST CIRCUIT
OUTPUT
LOW-to-OFF
OFF-to-LOW
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
nOE INPUT
GND
V
V
GENERATOR
V
GND
V
OL
OH
CC
t
t
PLZ/
PHZ/
I
PULSE
SWITCH POSITION
t
PLH/
TEST
DEFINITIONS
R
C
R
Waveform 5. Load circuitry for switching times
Waveform 4. 3-State enable and disable times
t
t
L
L
T
PZL
PZH
t
= Load resistor
= Load capacitance includes jig and probe capacitance
= Termination resistance should be equal to Z
PHL
Test Circuit for switching times
outputs
enabled
2 < V
V
Open
V
M
GND
I
S
t
PLZ
1
R
t
PHZ
T
CC
D.U.T.
V
V
CC
X
V
2.7–3.6V
Y
< 2.7V
74ALVCH16841
V
CC
outputs
disabled
V
O
C
L
OUT
2.7V
V
V
Product specification
t
CC
PZL
t
I
PZH
of pulse generators.
S
V
1
R
R
M
SV00906
SH00137
V
L
L
M
= 500
= 500
outputs
enabled
2 * V
Open
GND
CC