74HCT259PW,112 NXP Semiconductors, 74HCT259PW,112 Datasheet - Page 13
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74HCT259PW,112
Manufacturer Part Number
74HCT259PW,112
Description
IC 8BIT ADDRESSABL LATCH 16TSSOP
Manufacturer
NXP Semiconductors
Series
74HCTr
Datasheets
1.74HCT4046ADB112.pdf
(19 pages)
2.74HCT4046ADB112.pdf
(23 pages)
3.74HCT259N652.pdf
(11 pages)
Specifications of 74HCT259PW,112
Logic Type
D-Type, Addressable
Package / Case
16-TSSOP
Circuit
1:8
Output Type
Standard
Voltage - Supply
4.5 V ~ 5.5 V
Independent Circuits
1
Delay Time - Propagation
23ns
Current - Output High, Low
4mA, 4mA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Number Of Circuits
1
Logic Family
HCT
Polarity
Non-Inverting
High Level Output Current
- 4 mA
Low Level Output Current
5.2 mA
Propagation Delay Time
20 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2816-5
935188410112
935188410112
Philips Semiconductors
AC waveforms 74HCT
Test circuit for 74HCT
March 1988
handbook, full pagewidth
HCMOS family characteristics
C
R
(1) In Fig.9 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals
(2) For AC measurements: t
Fig.9
L
T
(SET, RESET and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual
active levels of the forcing signals are specified in the individual device data sheet.
=
=
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
load capacitance including jig and probe capacitance (see AC
CHARACTERISTICS for values).
termination resistance should be equal to the output impedance Z
the pulse generator.
OUTPUT
PRESET
CLOCK
RESET,
r
INPUT
INPUT
INPUT
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
GENERATOR
10%
1.3 V
PULSE
t su
t rem
1.3 V
t r
10%
1.3 V
t PLH
90%
t WH
max
Fig.10 Test circuit.
1.3 V
V I
90%
t h
, there is no constraint on t
1/f max
t TLH
t f
R T
13
t WL
o
D.U.T
V CC
t su
of
t PHL
V O
r
, t
f
with 50% duty factor.
C L
t h
FAMILY SPECIFICATIONS
t THL
MGK565
50 pF
MGK568
3 V
GND
3 V
GND
3 V
GND