74F402PC Fairchild Semiconductor, 74F402PC Datasheet
74F402PC
Specifications of 74F402PC
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74F402PC Summary of contents
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... CWG Control input inhibits feedback during check word transmission. The 74F402 is compatible with FAST devices and with all TTL families. Ordering Code: Order Number Package Number 74F402PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Logic Symbol FAST is a registered trademark of Fairchild Semiconductor Corporation. ...
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Unit Loading/Fan Out Pin Names Description S –S Polynomial Select Inputs 0 3 CWG Check Word Generate Input D/CW Serial Data/Check Word D Data Input Error Output ER RO Register Output CP Clock Pulse SEI Serial Expansion Input RFB Register ...
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Select Code Hex ...
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P P Select Code Applications In addition ...
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5 www.fairchildsemi.com ...
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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PLH D/CW PHL t Propagation Delay PLH PHL t Propagation Delay PLH PHL t Propagation Delay ...
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AC Operating Requirements Symbol Parameter t (H) Setup Time, HIGH or LOW S t (L) SEI (H) Hold Time, HIGH or LOW H t (L) SEI (H) Setup Time, HIGH or LOW ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...