74LV595PW,112 NXP Semiconductors, 74LV595PW,112 Datasheet
74LV595PW,112
Specifications of 74LV595PW,112
74LV595PW
935198290112
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74LV595PW,112 Summary of contents
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Rev. 03 — 21 April 2009 1. General description The 74LV595 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage register have ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Temperature range 74LV595N +125 C 74LV595D +125 C 74LV595DB +125 C 74LV595PW +125 C 5. Functional diagram Fig 1. Logic symbol Fig 3. Functional diagram 74LV595_3 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register; 3-state Name Description DIP16 plastic dual in-line package ...
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... NXP Semiconductors STAGE LATCH Fig 4. Logic diagram Fig 5. Timing diagram 74LV595_3 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register; 3-state STAGES FF0 Rev. 03 — 21 April 2009 74LV595 STAGE FF7 LATCH CP mna555 Q 7 Z-state Z-state Z-state Z-state mna556 © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74LV595 GND 8 001aaj970 Fig 6. Pin configuration DIP16, SO16 6.2 Pin description Table 2. Pin description Symbol Pin 15 parallel data output GND 8 Q7S SHCP 11 STCP 74LV595_3 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register; 3-state STCP ...
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... NXP Semiconductors 7. Functional description [1] Table 3. Function table Input SHCP STCP [ HIGH voltage state LOW voltage state high-impedance OFF-state. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage ...
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... NXP Semiconductors 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 10. Static characteristics Table 6. Static characteristics At recommended operating conditions ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions V LOW-level all outputs output voltage I = 100 standard driver outputs V CC bus driver outputs input leakage current GND I I OFF-state output current supply current ...
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... NXP Semiconductors 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t propagation delay SHCP to Q7S; see STCP to Qn; see Q7S; see enable time OE to Qn; see disable time OE to Qn; see dis 74LV595_3 Product data sheet 8-bit serial-in/serial-out or parallel-out shift register ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions t pulse width SHCP, HIGH or LOW; W see STCP, HIGH or LOW; see LOW; see set-up time DS to SHCP; see SHCP to STCP; see hold time DS to SHCP; see ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions f maximum SHCP or STCP; see max frequency and power dissipation V = GND capacitance [1] Typical values are measured the same as t and PLH PHL [3] Typical value measured ...
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... NXP Semiconductors SH CP input ST CP input Q n output Measurement points are given in V and V are typical output voltage drops that occur with the output load Fig 9. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time ...
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... NXP Semiconductors SH CP input output Measurement points are given in V and V are typical output voltage drops that occur with the output load Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the master reset to shift clock (SHCP) recovery time ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 13. Load circuit for measuring switching times Table 9. Test data ...
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... NXP Semiconductors 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP16: plastic shrink small outline package; 16 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT338-1 Fig 16. package outline (SOT338-1); (SSOP16) ...
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... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date 74LV595_3 20090421 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Abbreviations ...