AM29PDLI27H SPANSION [SPANSION], AM29PDLI27H Datasheet - Page 11
![no-image](/images/no-image-200.jpg)
AM29PDLI27H
Manufacturer Part Number
AM29PDLI27H
Description
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO Control
Manufacturer
SPANSION [SPANSION]
Datasheet
1.AM29PDLI27H.pdf
(68 pages)
- Current page: 11 of 68
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PIN DESCRIPTION
A22–A0
DQ15–DQ0 =
CE#
OE#
WE#
V
NC
RY/BY#
WP#/ACC
V
V
RESET#
June 30, 2003
SS
IO
CC
=
=
=
=
=
=
=
=
=
=
=
23-bit address bus for 128 Mb de-
vice. A9 supports 12 V autoselect in-
puts.
16-bit data inputs/outputs/float
Chip Enable Inputs
Output Enable Input
Write Enable
Device Ground
Pin Not Connected Internally
Ready/Busy output and open drain.
When RY/BY#= V
ready to accept read operations and
commands. When RY/BY#= V
the device is either executing an em-
bedded algorithm or the device is
executing a hardware reset opera-
tion.
Write Protect/Acceleration Input.
When WP/ACC#= V
and lowest two 4K-word sectors are
write protected regardless of other
sector protection configurations.
When WP/ACC#= V
are unprotected unless the DYB or
PPB is programmed. When
WP/ACC#= 12V, program and erase
operations are accelerated.
Input/Output Buffer Power Supply
(1.65 V to 1.95 V or 2.7 V to 3.6 V)
Chip Power Supply
(2.7 V to 3.6 V or 2.7 to 3.3 V)
Hardware Reset Pin
A D V A N C E
IH
, the device is
IL
IH
, the highest
, these sector
OL
Am29PDL127H
,
I N F O R M A T I O N
LOGIC SYMBOL
23
A22–A0
CE#
OE#
WE#
WP#/ACC
RESET#
V
IO
(V
CCQ
)
DQ15–DQ0
RY/BY#
16
9
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