74CBTLV1G125GW,125 NXP Semiconductors, 74CBTLV1G125GW,125 Datasheet

IC SINGLE BUS SWITCH 5-TSSOP

74CBTLV1G125GW,125

Manufacturer Part Number
74CBTLV1G125GW,125
Description
IC SINGLE BUS SWITCH 5-TSSOP
Manufacturer
NXP Semiconductors
Series
74CBTLVr
Type
FET Bus Switchr
Datasheet

Specifications of 74CBTLV1G125GW,125

Package / Case
SC-70-5, SC-88A, SOT-323-5, SOT-353, 5-TSSOP
Circuit
1 x 1:1
Independent Circuits
1
Voltage Supply Source
Single Supply
Voltage - Supply
2.3 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
CBTLV
On Resistance (max)
11 Ohms
Propagation Delay Time
0.16 ns
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Function
Bus Switch
High Level Output Current
- 128 mA
Low Level Output Current
128 mA
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V, 3.3 V
Organization
1 x 1:1
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.3 V
Logic Type
CMOS
Number Of Circuits
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Output High, Low
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4833-2
74CBTLV1G125GW,125
74CBTLV1G125GW-G
74CBTLV1G125GW-G
935280319125
1. General description
2. Features and benefits
The 74CBTLV1G125 provides a single high-speed line switch. The switch is disabled
when the output enable (OE) input is high.
To ensure the high-impedance OFF-state during power up or power down, OE should be
tied to the V
by the current-sinking capability of the driver.
Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall
times across the entire V
This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.
74CBTLV1G125
Single bus switch
Rev. 2 — 29 July 2010
Supply voltage range from 2.3 V to 3.6 V
High noise immunity
Complies with JEDEC standard:
ESD protection:
5 Ω switch connection between two ports
Rail to rail switching on data I/O ports
CMOS low power consumption
Latch-up performance meets requirements of JESD78 Class I
I
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
OFF
OFF
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
circuitry provides partial power down mode operation
circuitry disables the output, preventing the damaging backflow current through
CC
through a pull-up resistor. The minimum value of the resistor is determined
CC
range from 2.3 V to 3.6 V.
Product data sheet
OFF
.

Related parts for 74CBTLV1G125GW,125

74CBTLV1G125GW,125 Summary of contents

Page 1

Single bus switch Rev. 2 — 29 July 2010 1. General description The 74CBTLV1G125 provides a single high-speed line switch. The switch is disabled when the output enable (OE) input is high. To ensure the high-impedance OFF-state during power ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74CBTLV1G125GW −40 °C to +125 °C −40 °C to +125 °C 74CBTLV1G125GV −40 °C to +125 °C 74CBTLV1G125GM −40 °C to +125 °C 74CBTLV1G125GF −40 °C to +125 °C 74CBTLV1G125GN −40 °C to +125 °C 74CBTLV1G125GS 4 ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74CBTLV1G125 GND 001aad715 Fig 3. Pin configuration SOT353-1 and SOT753 6.2 Pin description Table 3. Pin description Symbol Pin SOT353-1, SOT753 SOT886, SOT891, SOT1115 and SOT1202 GND n. Functional description 7.1 Function table [1] Table 4. Function table Output enable input OE ...

Page 4

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW I input clamping current IK I switch clamping current SK I switch current ...

Page 5

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I power-off leakage current OFF I supply current CC ΔI additional supply current CC C input capacitance I C switch capacitance sw = −40 °C to +125 °C T amb V HIGH-level input voltage IH V LOW-level input voltage ...

Page 6

... NXP Semiconductors GND Fig 6. Test circuit for measuring OFF-state leakage current Fig 8. Test circuit for measuring ON-resistance 74CBTLV1G125 Product data sheet 001aad716 Fig GND All information provided in this document is subject to legal disclaimers. Rev. 2 — 29 July 2010 74CBTLV1G125 Single bus switch V CC ...

Page 7

... NXP Semiconductors (Ω 125 °C (1) T amb = 85 °C (2) T amb = 25 °C (3) T amb = −40 °C (4) T amb 2 mA (Ω 125 °C (1) T amb = 85 °C (2) T amb = 25 °C (3) T amb = −40 °C (4) T amb 2 mA Fig 9. Switch ON-resistance as a function of input voltage at V ...

Page 8

... NXP Semiconductors (Ω 125 °C (1) T amb = 85 °C (2) T amb = 25 °C (3) T amb = −40 °C (4) T amb 3 mA (Ω 125 °C (1) T amb = 85 °C (2) T amb = 25 °C (3) T amb = −40 °C (4) T amb 3 mA Fig 10. Switch ON-resistance as a function of input voltage at V ...

Page 9

... NXP Semiconductors 11. Dynamic characteristics Table 9. Dynamic characteristics GND = 0 V; see Figure 13. Symbol Parameter Conditions t propagation delay see enable time see disable time see dis [1] All typical values are measured at T [2] The propagation delay is the calculated RC time constant of the maximum on-state resistance of the switch and the load capacitance, when driven by an ideal voltage source (zero output impedance) ...

Page 10

... NXP Semiconductors LOW-to-OFF OFF-to-LOW HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and Fig 12. Enable and disable times Table 11. Measurement points Supply voltage Input 0.5 × 2.7 V 0.5 × 3.6 V 74CBTLV1G125 Product data sheet input V M GND t PLZ V CC ...

Page 11

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance Test voltage for switching times. EXT Fig 13. Test circuit for measuring switching times Table 12. ...

Page 12

... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION IEC SOT353-1 Fig 14 ...

Page 13

... NXP Semiconductors Plastic surface-mounted package; 5 leads DIMENSIONS (mm are the original dimensions) UNIT 0.100 1.1 0.40 0.26 mm 0.013 0.9 0.25 0.10 OUTLINE VERSION IEC SOT753 Fig 15. Package outline SOT753 74CBTLV1G125 Product data sheet scale 3.1 1.7 3.0 0.6 0.95 2.7 1.3 2.5 ...

Page 14

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 15

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 17 ...

Page 16

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 17

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 18

... NXP Semiconductors 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 14. Revision history Document ID Release date 74CBTLV1G125 v.2 20100729 • ...

Page 19

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 20

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74CBTLV1G125 Product data sheet 16 ...

Page 21

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 7.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 12 Waveforms ...

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