ISPGAL22V10 LATTICE [Lattice Semiconductor], ISPGAL22V10 Datasheet
ISPGAL22V10
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ISPGAL22V10 Summary of contents
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... State Machine Control — High Speed Graphics Processing — Software-Driven Hardware Configuration • ELECTRONIC SIGNATURE FOR IDENTIFICATION DESCRIPTION The ispGAL22V10, at 7.5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable ( floating gate technology to provide the industry's first in-system programmable 22V10 device. E fers high speed (< ...
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... Industrial Grade Specifications PART NUMBER DESCRIPTION ispGAL22V10C Device Name ispGAL22V10B Speed (ns Low Power Power Specifications ispGAL22V10 ...
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... OUTPUT LOGIC MACROCELL (OLMC) OUTPUT LOGIC MACROCELL CONFIGURATIONS Each of the Macrocells of the ispGAL22V10 has two primary func- tional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (SO and S1), which are nor- mally controlled by the logic compiler ...
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... REGISTERED MODE ACTIVE LOW COMBINATORIAL MODE ACTIVE LOW Specifications ispGAL22V10 ACTIVE HIGH ACTIVE HIGH ...
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... LOGIC DIAGRAM / JEDEC FUSE MAP 0000 0044 . . . 0396 0440 . . . . 0880 3 0924 . . . . . 1452 4 1496 . . . . . . 2112 5 2156 . . . . . . . 2860 6 2904 . . . . . . . 3608 7 3652 . . . . . . 4268 9 4312 . . . . . 4840 10 4884 . . . . 5324 11 5368 . . . 5720 12 5764 13 5828, 5829 ... Byte 7 Byte 6 Byte 5 Byte Specifications ispGAL22V10 PLCC & SSOP Package Pinout ...
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... Supply Current f toggle 1) The leakage current is due to the internal pull-up on all pins (except SDI on ispGAL22V10C). See Input Buffer section for more information. 2) The leakage current is due to the internal pull-down on the SDI pin (ispGAL22V10C only). See Input Buffer section for more information. ...
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... Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section. CAPACITANCE ( 1.0 MHz) A SYMBOL PARAMETER C Input Capacitance I C I/O Capacitance I/O *Characterized but not 100% tested. Specifications ispGAL22V10C Specifications ispGAL22V10 Over Recommended Operating Conditions MIN. MAX. 6.5 111 111 MAXIMUM* UNITS ispGAL22V10B COM ...
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... OUTPUT Input or I/O to Output Enable/Disable CLK (w/o fdbk) Clock Width INPUT or I/O FEEDBACK DRIVING CLK REGISTERED OUTPUT Synchronous Preset Specifications ispGAL22V10 INPUT or VALID INPUT I/O FEEDBACK t pd CLK REGISTERED OUTPUT t en CLK REGISTERED FEEDBACK INPUT or I/O FEEDBACK DRIVING ...
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... Output Load Conditions (see figure) Test Condition 300 B Active High Active Low 300 C Active High Active Low 300 Specifications ispGAL22V10 su+ co) CLK GND to 3.0V 3ns 10% – 90% 1.5V 1.5V See Figure FROM OUTPUT (O/Q) UNDER TEST ...
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... All input and I/O pins (except SDI on the ispGAL22V10C) also have built-in active pull-ups result, floating inputs will float to a TTL high (logic 1). The SDI pin on the ispGAL22V10C has a built-in pull-down to keep the device out of the programming state if the pin is not actively driven. However, Lattice Semicon- ductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground ...
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... Device Pin Reset to Logic "0" asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the ispGAL22V10. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time nor- mal system operation, avoid clocking the device until all input and feedback path setup times have been met ...
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... TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Normalized Tpd vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Normalized Tpd vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) Delta Tpd Outputs 0 -0.25 -0.5 -0. Number of Outputs Switching Delta Tpd vs Output Loading Ouput Loading (pF) Specifications ispGAL22V10 Normalized Tco vs Vcc 1 ...
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... TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS Vol vs Iol 3 2.5 2 1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00 Iol (mA) Normalized Icc vs Vcc 1.2 1.1 1 0.9 0.8 4.50 4.75 5.00 5.25 5.50 Supply Voltage (V) Delta Icc vs Vcc 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 Vin (V) Specifications ispGAL22V10 Voh vs Ioh 0.00 10.00 20.00 30.00 40.00 50.00 60.00 Ioh(mA) Normalized Icc vs Temp 1.3 1.2 1.1 1 0.9 0.8 0.7 -55 - 100 125 Temperature (deg. C) ...
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... Specifications ispGAL22V10 14 Notes ...
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Copyright © 1997 Lattice Semiconductor Corporation CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ...