ISPGAL22V10 LATTICE [Lattice Semiconductor], ISPGAL22V10 Datasheet - Page 11

• Manufacturer Part Number: ISPGAL22V10
• Description: In-System Programmable E2CMOS PLD
• Manufacturer: LATTICE [Lattice Semiconductor]

Circuitry within the ispGAL22V10 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (tpr, 1 s MAX). As a result, the
state on the registered output pins (if they are enabled) will be
either high or low on power-up, depending on the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. The
timing diagram for power-up is shown below. Because of the
POWER-UP RESET
INPUT/OUTPUT EQUIVALENT SCHEMATICS
(Vref Typical = 3.2V)
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
(SDI on ispGAL22V10C Only)
Vcc
on ispGAL22V10C)
Circuit (Except SDI
Pull-down Resistor
Input
Active Pull-up
INTERNAL REGISTER
OUTPUT REGISTER
OUTPUT REGISTER
Vref
ACTIVE HIGH
ACTIVE LOW
Q - OUTPUT
Vcc
C L K
V c c
Vcc
Vcc (min.)
11
t
asynchronous nature of system power-up, some conditions must
be met to provide a valid power-up reset of the ispGAL22V10.
First, the Vcc rise must be monotonic. Second, the clock input
must be at static TTL level as shown in the diagram during power
up. The registers will reset within a maximum of tpr time. As in nor-
mal system operation, avoid clocking the device until all input and
feedback path setup times have been met. The clock must also
meet the minimum pulse width requirements.
pr
Specifications ispGAL22V10
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
Device Pin
Reset to Logic "0"
t
wl
Feedback
Tri-State
Control
t
su
Vcc
Output
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
(Vref Typical = 3.2V)
PIN
PIN