92HD66B IDT [Integrated Device Technology], 92HD66B Datasheet - Page 71

• Manufacturer Part Number: 92HD66B
• Description: FOUR CHANNEL HD AUDIO CODECS
• Manufacturer: IDT [Integrated Device Technology]

92HD66B
FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
Field Name
Mono0
PhAdj
Rate
Field Name
Rsvd
SDMSettleDisable
SDMCoeffSel
SDMLFHalf
Reg
Get
Set
6.7.21. AFG (NID = 01h): DACMode
Byte 4 (Bits 31:24)
Bits
4
DMic0 mono select: 0 = stereo operation, 1 = mono operation (left channel du-
plicated to the right channel).
3:2
Selects what phase of the DMic clock the data should be latched:
0h = left data rising edge/right data falling edge
1h = left data center of high/right data center of low
2h = left data falling edge/right data rising edge
3h = left data center of low/right data center of high
1:0
Selects the DMic clock rate:
0h = 4.704MHz
1h = 3.528MHz
2h = 2.352MHz
3h = 1.176MHz.
Bits
31:8
Reserved.
7
SDM wait-to-settle disable:
1 = at mute, the SDM switches to the mute pattern immediately
0 = at mute, the SDM switches to the mute pattern after settling (can take up to
~45ms)
6
DAC SDM coefficient select (stages 1, 2, 3):
1 = 1/16, 1/2, 1/4
0 = 1/16, 1/4, 1/2
5
DAC SDM local feedback coefficient select: 1 = 1/4096, 0 = 1/2048.
Byte 3 (Bits 23:16)
R/W
RW
RW
RW
R/W
R
RW
RW
RW
F8000h
Default
0h
0h
2h
Default
000000h
0h
0h
0h
71
Byte 2 (Bits 15:8)
Reset
POR
POR
POR
Reset
N/A (Hard-coded)
POR
POR
POR
Byte 1 (Bits 7:0)
780h
V 1.0 2/12
92HD66B