ZL50012/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50012/GDC Datasheet
ZL50012/GDC
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ZL50012/GDC Summary of contents
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... Figure 1 - ZL50012 Functional Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2004, Zarlink Semiconductor Inc. All Rights Reserved. Flexible 512-ch Digital Switch Ordering Information ZL50012/QCC ZL50012/GDC -40°C to +85°C • Per-channel high impedance output control • Per-channel message mode • ...
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Applications • Small and medium digital switching platforms • Access Servers • Time Division Multiplexers • Computer Telephony Integration • Digital Loop Carriers Description The device has sixteen ST-BUS inputs (STi0-15) and sixteen ST-BUS outputs (STo0-15 non-blocking ...
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - ZL50012 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - FPi and CKi Input Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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NC 122 NC 123 A2 124 A3 125 A4 126 VSS 127 VDD 128 A5 129 A6 130 A7 131 A8 132 A9 133 A10 134 A11 135 VSS 136 VDD 137 STi0 138 STi1 139 STi2 140 STi3 ...
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PINOUT DIAGRAM: (as viewed through top of package) A1 corner identified by metallized marking, mould indent, ink dot or right-angled corner 1 A ODE B CKo2 C STo2 D STo3 E STo5 F STo6 G STOHZ 6 H STo9 J ...
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Pin Description LQFP Pin LBGA Ball Number Number 10, 23, 33, D5, D6, D7 43, 48, 58, E9 68, 78, 92, F4, F9 102, 113, G4 127, 136, H4 146, 156 J6, J7 18, 21, D4, D9 32, ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number C10 14, 15, 19 C9, C8 A6, A5, B6, B5, C7 30, 31 C4, ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number D2, C2, C1 E2, E1, F1 H3, H1, H2 L2, ...
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Pin Description (continued) LQFP Pin LBGA Ball Number Number 115 M12 116 H10 117, 118 M10, M11 123 - 125 L10, L11, K11 128 - 130 K10, L12, K12 131 - 134 J11, J10, J9, J12 137 - 139 H9, ...
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Device Overview The device uses the ST-BUS input frame pulse and the ST-BUS input clock to define the input frame boundary and timing for the ST-BUS input streams with various data rates (2.048 Mb/s, 4.096 Mb/s and/or 8.192 Mb/s). ...
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The device also accepts positive or negative input frame pulse and ST-BUS input clock formats via the programming of the FPINP and CKINP bits in the Internal Mode Selection (IMS) register. By default, the device accepts the negative input clock ...
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ST-BUS Input Timing When the negative input frame pulse and negative input clock formats are used, the input frame boundary is defined by the falling edge of the CKi input clock while the FPi is low. When the input ...
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ST-Bus Output Data Rate and Output Timing The device has sixteen ST-Bus serial data outputs. Any of the sixteen outputs can be programmed to deliver different data rates at 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s. 2.2.1 ST-Bus Output ...
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The device also delivers positive or negative output frame pulse and ST-BUS output clock formats via the programming of the FP0P, FP1P, FP2P, CK0P, CK1P and CK2P bits in the Internal Mode Selection (IMS) register. By default, the device delivers ...
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FPo1 FP1P = 0 FPo1 FP1P =1 CKo1 (8.192 MHz) CK1P = 0 CKo1 (8.192 MHz) CK1P = 1 Figure 11 - FPo1 and CKo1 Output Timing when the CKFP1 bit = 1 FPo2 FP2P = 0 FPo2 FP2P = ...
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ST-BUS Output Timing By default, the output frame boundary is defined by the falling edge of the CKo0, CKo1 or CKo2 output clock while the FPo0, FPo1 or FPo2 output frame pulse goes low respectively. When the output data ...
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Serial Data Input Delay and Serial Data Output Offset Various registers are provided to adjust the input and output delays for every input and every output data stream. The input and output channel delay can vary from 0 to ...
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Fractional Input Bit Delay Programming In addition to the input bit delay feature, the device allows users to change the sampling point of the input bit. By default, the sampling point is at 3/4 bit. Users can change the ...
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Output Bit Delay Programming This feature is used to delay the output data bit of individual output streams with respect to the output frame boundary. Each output stream can have its own bit delay value. By default, all output ...
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External High Impedance Control, STOHZ The STOHZ outputs are provided to control the external tristate ST-BUS drivers for per-channel high impedance operations. The STOHZ outputs are sent out in 32 128 ...
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Data Delay Through The Switching Paths To maintain the channel integrity in the constant delay mode, the usage of the input channel delay and output channel delay modes affect the data delay through various switching paths due to additional ...
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By default, when the input channel delay and output channel delay are set to zero, the data throughput delay (T) is frames + (m-n). Figure 21 shows the throughput delay when the input Ch0 is switched to ...
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When the input channel delay and the output channel delay are enabled, the data throughput delay is frames - α + β + (m-n). Figure 24 shows the data throughput delay when the input Ch0 is switched ...
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Connection Memory Description The connection memory is 12-bit wide. There are 512 memory locations to support the ST-BUS serial outputs STo0-15. The address of each connection memory location corresponds to an output destination stream number and an output channel ...
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Bit Error Rate (BER) Test The ZL50012 has one on-chip BER transmitter and one BER receiver. The transmitter can transmit onto a single STo output stream only. The transmitter provides a BER sequence (2 from any channel in the ...
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Quadrant frame programming By programming the input stream control registers (SICR0 to 15), users can divide one frame of input data into four quadrant frames and can force the Least Significant Bit (LSB, bit 0 in Figure 7 on ...
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Microprocessor Port The device supports the non-multiplexed microprocessor. The microprocessor port consists of a 16-bit parallel data bus (D0 to 15), a 12-bit address bus (A0 to 11) and four control signals (CS, DS, R/W and DTA). The parallel ...
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Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described ...
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Register Address Mapping External Address A11 - A0 000 H 001 H 010 H 011 H 012 H 030 H 031 H 032 H 100 H 101 H 102 H 103 H 104 H 105 H 106 H 107 ...
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ZL50012 External CPU Address Access A11 - A0 11B R/W Stream13 Input Delay Register, SIDR13 H 11C R/W Stream14 Input Control Register, SICR14 H 11D R/W Stream14 Input Delay Register, SIDR14 H 11E R/W Stream15 Input Control Register, SICR15 H ...
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Detail Register Description External Read/Write Address: 000 H Reset Value: 0000 FBD CKIN CKIN Bit Name Unused Reserved. In normal functional mode, these bits MUST ...
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External Read/Write Address: 000 H Reset Value: 0000 FBD CKIN CKIN CKIN Bit Name 3 OSB Output Stand By Bit: This bit enables the STo0 - 15 and ...
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External Read/Write Address: 001 H Reset Value: 0000 CKINP FPINP Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero. 11 CKINP ...
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External Read/Write Address: 001 H Reset Value: 0000 CKINP FPINP Bit Name 0 MBPS Memory Block Programming Start: A zero to one transition of this bit starts the memory block ...
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External Read/Write Address: 011 H Reset Value: 0000 Bit Name Unused Reserved. In normal functional mode, these bits MUST be set to zero ...
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External Read/Write Address: 100 , 102 , 104 H H Reset Value: 0000 SICR0 SICR1 SICR2 SICR3 SICR4 0 ...
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External Read/Write Address: 100 , 102 , H H Reset Value: 0000 SICR0 SICR1 SICR2 SICR3 SICR4 0 0 ...
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External Read/Write Address: 110 , 112 , 114 H H Reset Value: 0000 SICR8 SICR9 SICR10 SICR11 0 0 ...
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External Read/Write Address: 110 , 112 , H H Reset Value: 0000 SICR8 SICR9 SICR10 SICR11 SICR12 0 0 ...
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External Read/Write Address: 101 , 103 , H H Reset Value: 0000 SIDR0 SIDR1 SIDR2 SIDR3 SIDR4 0 0 ...
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External Read/Write Address: 111 , 113 , H H Reset Value: 0000 SIDR8 SIDR9 SIDR10 SIDR11 ...
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External Read/Write Address: 200 , 202 , H H Reset Value: 0000 SOCR0 SOCR1 SOCR2 SOCR3 SOCR4 0 0 ...
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External Read/Write Address: 210 , 212 , H H Reset Value: 0000 SOCR8 SOCR9 SOCR10 SOCR11 ...
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External Read/Write Address: 201 , 203 , H H Reset Value: 0000 SOOR0 SOOR1 SOOR2 SOOR3 SOOR4 0 0 ...
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External Read/Write Address: 211 , 213 , H H Reset Value: 0000 SOOR8 STO8C D6 SOOR9 STO9C D6 SOOR10 STO10 CD6 SOOR11 ...
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Memory Address Mappings When A11 is high, the data or the connection memory can be accessed by the microprocessor port. The Bit 0 to Bit 2 in the control register determine the access to the data or connection memory ...
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Connection Memory Bit Assignment When the CMM bit (Bit0) is zero, the connection is in normal switching mode. When the CMM bit is one, the connection memory is in special transmission mode SSA3 SSA2 SSA1 Bit ...
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Absolute Maximum Ratings* Parameter 1 I/O Supply Voltage 2 Input Voltage 3 Input Voltage (5 V tolerant inputs) 4 Continuous Current at digital outputs 5 Package power dissipation 6 Storage temperature * Exceeding these values may cause permanent damage. Functional ...
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AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. † AC Electrical Characteristics - FPi ...
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FPi t CKi Input Frame Boundary Figure 25 - Frame Pulse Input and Clock Input Timing Diagram † AC Electrical Characteristics - Frame Boundary Timing with Input Clock Cycle-to-cycle Variation Characteristic 1 CKi Input Clock cycle-to-cycle variation † Characteristics are ...
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AC Electrical Characteristics - Frame Boundary Timing with Input Frame Pulse Cycle-to-cycle Variation Characteristic 1 FPi Input Frame Pulse cycle-to-cycle variation † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25° ...
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FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) Input Frame Boundary t FBOS FPo2 CKo2 (32.768 MHz) FPo2 or FPo1 CKo2 or FPo1 (16.384 MHz) FPo1 or FPo0 CKo1 or CKo0 (8.192 MHz) FPo0 CKo0 (4.096 ...
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AC Electrical Characteristics - FPo0 and CKo0 Timing when CKFP0 = 0 Characteristic 1 FPo0 Output Pulse Width 2 FPo0 Output Delay from the CKo0 falling edge to the output frame boundary 3 FPo0 Output Delay from the output ...
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AC Electrical Characteristics - FPo1 and CKo1 Timing when CKFP1 = 0 Characteristic 1 FPo1 Output Pulse Width 2 FPo1 Output Delay from the CKo1 falling edge to the output frame boundary 3 FPo1 Output Delay from the output ...
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AC Electrical Characteristics - FPo2 and CKo2 Timing when CKFP2 = 0 Characteristic 1 FPo2 Output Pulse Width 2 FPo2 Output Delay from the CKo2 falling edge to the output frame boundary 3 FPo2 Output Delay from the output ...
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AC Electrical Characteristics - ST-BUS Input Timing Characteristic 1 STi Setup Time 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s 2 STi Hold Time 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s † Characteristics are over recommended operating conditions unless otherwise stated. ° ...
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AC Electrical Characteristics - ST-BUS Output Timing Characteristic 1 STo Delay - Active to Active @2.048 Mb/s @4.096 Mb/s @8.192 Mb/s † Characteristics are over recommended operating conditions unless otherwise stated. ° ‡ Typical figures are ...
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AC Electrical Characteristics - ST-BUS Output Tristate Timing Characteristic 1 STo Delay - Active to High-Z STo Delay - High-Z to Active 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s 2 Output Driver Enable (ODE) Delay - High-Z to Active 2.048 ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 DS delay from the rising edge of DTA to the falling edge ...
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AC Electrical Characteristics - JTAG Test Port and Reset Pin Timing Characteristic 1 TCK Clock Period 2 TCK Clock Pulse Width High 3 TCK Clock Pulse Width Low 4 TMS Set-up Time 5 TMS Hold Time 6 TDi Input ...
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Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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Zarlink Semiconductor 2002 All rights reserved ISSUE 213834 ACN 213740 11Dec02 15Nov02 DATE APPRD. Package Code Previous package codes ...
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