ZL50012/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50012/GDC Datasheet - Page 30

• Manufacturer Part Number: ZL50012/GDC
• Description: Flexible 512-ch Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

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4.2
The ZL50012 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a four-
bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP
Controller is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to
select the test data register that may operate while the instruction is current and to define the serial test data
register path that is used to shift data between TDI and TDO during data register scanning.
4.3
As specified in IEEE 1149.1, the ZL50012 JTAG Interface contains three test data registers:
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4.4
A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149 test interface.
Test Data Input (TDi) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDo) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDO. The data out of the
TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDO driver is set to a high impedance state.
Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven
from an external source.
The Boundary-Scan Register - The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the ZL50012 core logic.
The Bypass Register - The Bypass register is a single stage shift register that provides a one-bit path from
TDI to its TDO.
The Device Identification Register - The JTAG device ID for the ZL50012 is 0C35C14B
Version<31:28>:
Part No. <27:12>:
Manufacturer ID<11:1>: 0001 0100 101
LSB<0>:
Instruction Register
Test Data Register
BSDL
0000
1
1100 0011 0101 1100
Zarlink Semiconductor Inc.
ZL50012
33
H
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Data Sheet