ZL50012/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50012/GDC Datasheet - Page 35

• Manufacturer Part Number: ZL50012/GDC
• Description: Flexible 512-ch Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

15 - 12
3 - 1
15
External Read/Write Address: 001
0
Bit
Reset Value: 0000
10
11
9
8
7
6
5
4
14
0
BPD2 - 0
Unused
CKINP
FPINP
Name
CK2P
CK1P
CK0P
FP2P
FP1P
FP0P
13
0
H
12
0
Reserved. In normal functional mode, these bits MUST be set to zero.
ST Bus Clock Input (CKi) Polarity.
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
Frame Pulse Input (FPi) Polarity.
When this bit is low, the input frame pulse FPi should have the negative frame pulse
format. When this bit is high, the input frame pulse FPi should have the positive frame
pulse format.
ST Bus Clock Output (CKo2) Polarity.
When this bit is low, the output clock CKo2 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo2 rising edge aligns with the
frame boundary.
Frame Pulse Output (FPo2) Polarity.
When this bit is low, the output frame pulse FPo2 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo2 has the positive frame pulse format.
ST Bus Clock Output (CKo1) Polarity.
When this bit is low, the output clock CKo1 falling edge aligns with the frame bound-
ary. When this bit is high, the output clock CKo1 rising edge aligns with the frame
boundary.
Frame Pulse Output (FPo1) Polarity.
When this bit is low, the output frame pulse FPo1 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo1 has the positive frame pulse format.
ST Bus Clock Output (CKo0) Polarity.
When this bit is low, the output clock CKo0 falling edge aligns with the frame
boundary. When this bit is high, the output clock CKo0 rising edge aligns with the
frame boundary.
Frame Pulse Output (FPo0) Polarity.
When this bit is low, the output frame pulse FPo0 has the negative frame pulse format.
When this bit is high, the output frame pulse FPo0 has the positive frame pulse format.
Block Programming Data: These bits refer to the value to be loaded into the connec-
tion memory. Whenever the memory block programming feature is activated. After the
MBPE bit in the control register is set to high and the MBPS bit is set to high, the con-
tents of the bits BPD0 to BPD2 are loaded into Bit 0 to Bit 2 of the connection memory.
Bit 3 to Bit 11 of the connection memory are zeroed.
Table 16 - Internal Mode Selection (IMS) Register Bits
CKINP
11
H
FPINP
10
CK2P
9
Zarlink Semiconductor Inc.
ZL50012
FP2P
8
38
CK1P
7
Description
FP1P
6
CK0P
5
FP0P
4
BPD
3
2
BPD
2
1
BPD
Data Sheet
1
0
MBPS
0