ZL50012/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50012/GDC Datasheet - Page 19

• Manufacturer Part Number: ZL50012/GDC
• Description: Flexible 512-ch Digital Switch
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.3
Various registers are provided to adjust the input and output delays for every input and every output data stream.
The input and output channel delay can vary from 0 to 31, 0 to 63 and 0 to 127 channel(s) for the 2.048 Mb/s,
4.096 Mb/s and 8.192 Mb/s modes respectively.
The input and output bit delay can vary from 0 to 7 bits. The fractional input bit delay can vary from 1/4, 1/2, 3/4 to
4/4 bit. The fractional output bit advancement can vary from 0, 1/4, 1/2 to 3/4 bit.
2.3.1
This feature allows each input stream to have a different input frame boundary with respect to the input frame
boundary defined by the FPi and CKi. By default, all input streams have channel delay of zero such that Ch0 is the
first channel that appears after the input frame boundary (see Figure 15).
The input channel delay programming is enabled by setting Bit 3 to 9 in the Stream Input Delay Register (SIDR).
The input channel delay can vary from 0 to 31, 0 to 63 and 0 to 127 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s
modes respectively.
2.3.2
In addition to the input channel delay programming, the input bit delay programming feature provides users with
more flexibility when designing the switch matrices at high speed, in which the delay lines are easily created on
PCM highways which are connected to the switch matrix cards.
By default, all input streams have zero bit delay such that Bit 7 is the first bit that appears after the input frame
boundary, see Figure 16. The input delay is enabled by Bit 0 to 2 in the Stream Input Delay Registers (SIDR). The
input bit delay can vary from 0 to 7 bits.
Channel Delay = 2
Channel Delay = 0
Channel Delay = 1
Note: X = 0 to 15
Serial Data Input Delay and Serial Data Output Offset
Input Channel Delay Programming
Input Bit Delay Programming
Input Frame Boundary
(Default)
STiX
STiX
STiX
FPi
3
3
3
2
2
2
1 0
1 0
1 0
Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively
7
7
7
6
6
6
Last Channel -1
Figure 15 - Input Channel Delay Timing Diagram
Last Channel
5
5
5
Ch 0
Delay = 1
4
4
4
3
3
3
2
2
2
1 0
1 0
1 0
Delay = 2
7
7
7
Zarlink Semiconductor Inc.
6
6
6
Last Channel
5
5
5
Ch 1
Ch 0
ZL50012
4
4
4
3
3
3
22
2
2
2
1 0
1 0
1 0
7
6
5
Ch0
4
3
6
6
Last Channel -1
Last Channel -2
2
5
5
1 0
4
4
3
3
2
2
1 0
1 0
7
7
7
Last Channel -1
6
6
Last Channel -2
6
Last Channel
5
5
5
4
4
4
3
3
3
2
2
2
1 0
1 0
1 0
Data Sheet
7 6
7 6
7 6