ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet
ZL50019
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ZL50019 Summary of contents
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... REF_FAIL1 REF_FAIL2 REF_FAIL3 OSC_EN OSC Figure 1 - ZL50019 Functional Block Diagram Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912, France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08 Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved. ...
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... PBX and IP-PBX • Small and medium digital switching platforms • Remote access servers and concentrators • Wireless base stations and controllers • Multi service access platforms • Digital Loop Carriers • Computer Telephony Integration ZL50019 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Description The ZL50019 is a maximum 2,048 x 2,048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be independently programmed to operate at any of the following data rates: 2 ...
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... Input Jitter Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 15.3 Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16.0 DPLL Specific Functions and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16.1 Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16.2 Maximum Time Interval Error (MTIE 16.3 Phase Alignment Speed (Phase Slope 16.4 Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 16.5 Single Period Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 16.6 Multiple Period Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ZL50019 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 25.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 25.1 Memory Address Mappings 25.2 Connection Memory Low (CM_L) Bit Assignment 25.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 26.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 26.1 OSCi Master Clock Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 26.1.1 External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 26.1.2 External Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 27.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 28.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ZL50019 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 1 - ZL50019 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - ZL50019 256-Ball PBGA (as viewed through top of package Figure 3 - ZL50019 256-Lead LQFP (top view Figure 4 - Input Timing when CKIN1 - 0 bits = “10” in the Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the Figure 6 - Input Timing when CKIN1 - 0 = “ ...
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... Table 3 - Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 4 - Delay for Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 5 - Connection Memory Low After Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6 - Connection Memory High After Block Programming Table 7 - ZL50019 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 8 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 9 - Generated Output Frequencies Table 10 - Values for Single Period Limits Table 11 - Multi-Period Hysteresis Limits ...
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... Table 51 - Address Map for Memory Locations (A13 = Table 52 - Connection Memory Low (CM_L) Bit Assignment when CMM = Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = Table 54 - Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ZL50019 List of Tables 8 Zarlink Semiconductor Inc. ...
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... Changes Summary Page Item 10 Figure 2, “ZL50019 256-Ball PBGA (as viewed through top of package) 11 Figure 3, “ZL50019 256-Lead LQFP (top view) 12 3.0, “Pin Description“ 19 4.0, “Device Overview“ 35 12.0, “Device Performance in Master Mode and Slave Modes“ 37 13.0, “Overall Operation of the DPLL“ ...
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... STOHZ2 T V STio28 STio29 STio31 STio30 Note: A1 corner identified by metallized marking. Note: Pinout is shown as viewed through top of package. Figure 2 - ZL50019 256-Ball PBGA (as viewed through top of package) ZL50019 STi26 STi24 NC NC STio22 V DD_ STi0 CKo0 ...
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... VDD_IO STi_22 250 VSS STi_23 252 STio_24 STio_25 254 STio_26 STio_27 256 Figure 3 - ZL50019 256-Lead LQFP (top view) ZL50019 176 174 172 170 168 166 164 162 160 158 156 154 152 150 ...
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... M5, M12, 209, 214, P3, P14, T1, 216, 218, T16 222, 223, 228, 230, 232, 235, 242, 251 ZL50019 Power Supply for the core logic: +1.8 V Power Supply for analog circuitry: +1.8 V Power Supply for I/O: +3.3 V DD_IO Power Supply for the CKo5 and CKo3 outputs: +3.3 V DD_IOA V Ground ...
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... T15 219, 225, 229, 236, 237 ZL50019 Test Mode Select (5 V-Tolerant Input with Internal Pull-up) JTAG signal that controls the state transitions of the TAP controller. This pin is pulled high by an internal pull-up resistor when it is not driven. Test Clock (5 V-Tolerant Schmitt-Triggered Input with Internal Pull-up) Provides the clock to the JTAG test logic ...
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... Input Clock Mode V-Tolerant Input with internal pull-down) These two pins should be tied together and are typically used to select CKi = 4.096 MHz operation. See Table 7, “ZL50019 Operating Modes” on page 36 for a detailed explanation. See Table 16, “Control Register (CR) Bits” on page 48 for CKi and FPi selection using the CKIN1 - 0 bits ...
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... B7, C7, B5, 170, 172, CKo0 - 5 J6, D6, H5 174, 227, 176, 221 ZL50019 ST-BUS/GCI-Bus Frame Pulse Outputs V-Tolerant Three-state Outputs) FPo0: 8 kHz frame pulse corresponding to the 4.096 MHz output clock of CKo0. FPo1: 8 kHz frame pulse corresponding to the 8.192 MHz output clock of CKo1. ...
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... Number B10 155 FPi B11 154 CKi ZL50019 Description ST-BUS/GCI-Bus Frame Schmitt-Triggered Input) This pin accepts the frame pulse which stays active for 61 ns, 122 ns or 244 ns at the frame boundary. The frame pulse frequency is 8 kHz. The frame pulse associated with the highest input or output data rate must be applied to this pin when the device is operating in Divided Slave mode or Master mode ...
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... K16, H16, 77, 78, J16, G16, 119, 120, F16 122, 124 ZL50019 Description Serial Input Streams V-Tolerant Inputs with Enabled Internal Pull-downs) The data rate of each input stream can be selected independently using the Stream Input Control Registers (SICR[n]). In the 2.048 Mbps mode, these pins accept serial TDM data streams at 2 ...
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... H13, H15, 94, 96, G12, G13 98, 99 ZL50019 Output Drive Enable (5 V-Tolerant Input with Internal Pull-up) This is the output enable control for STio0 - 31 and the output-driven-high control for STOHZ0 - 15. When it is high, STio0 - 31 and STOHZ0 - 15 are enabled. When it is low, STio0 - 31 are tristated and STOHZ0 - 15 are driven high ...
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... MHz reference signal. The on-chip DPLL also offers jitter attenuation, reference switching, reference monitoring, freerun and holdover functions. The jitter performance exceeds the Stratum 4E specification. The intrinsic jitter of all output clocks is less than 1 ns (except for the 1.544 MHz output). ZL50019 Motorola_Intel (5 V-Tolerant Input with Enabled Internal Pull-up) This pin selects the Motorola or Intel microprocessor interface to be connected to the device ...
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... Data Rates and Timing The ZL50019 has 32 serial data inputs and 32 serial data outputs. Each stream can be individually programmed to operate at 2.048 Mbps, 4.096 Mbps, 8.192 Mbps or 16.384 Mbps. Depending on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 µs frame. ...
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... Input Clock (CKi) and Input Frame Pulse (FPi) Timing The input clock for the ZL50019 can be arranged in one of three different ways. These different ways will be explained further in Section 12.1 to Section 12.3 on page 37. Depending on the mode of operation, the input clock, CKi, will be based on the highest data rate of either the input or both the input and output data rates. The user has to program the CKIN1 - 0 (bits the Control Register (CR) to indicate the width of the input frame pulse and the frequency of the input clock supplied to the device ...
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... FPINPOS = 1 FPi (122 ns) FPINP = 1 FPINPOS = 1 CKi (8.192 MHz) CKINP = 0 CKi (8.192 MHz) CKINP = 1 Channel 0 STi (4.096 Mbps) Figure 5 - Input Timing when CKIN1 - 0 bits = “01” in the CR ZL50019 Channel Channel Zarlink Semiconductor Inc. Data Sheet ...
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... Output Timing Generation The ZL50019 generates frame pulse and clock timing. There are five output frame pulse pins (FPo0 - 3, 5) and six output clock pins (CKo0 - 5). All output frame pulses are 8 kHz output signals. By default, the output frame boundary is defined by the falling edge of the CKo0, while FPo0 is low. At the output frame boundary, the CKo1, CKo2 and CKo3 output clocks will by default have a falling edge, while FPo1, FPo2 and FPo3 will be low ...
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... Output Clock and Frame Pulse Selection Register (OCFSR). By default, the device delivers the negative output clock format. The ZL50019 can also deliver GCI-Bus format output frame pulses by programming bits of the Output Clock and Frame Pulse Selection Register (OCFSR). As there is a separate bit setting for each frame pulse output, some of the outputs can be set to operate in ST-BUS mode and others in GCI-Bus mode ...
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... Figure 7 - Output Timing for CKo0 and FPo0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 0 CKOFPO1EN = 1 FPO1P = 0 FPO1POS = 1 CKOFPO1EN = 1 FPO1P = 1 FPO1POS = 1 CKOFPO1EN = 1 CKO1P = 0 CKo1 = 8.192 MHz CKOFPO1EN = 1 CKO1P = 1 CKo1 = 8.192 MHz Figure 8 - Output Timing for CKo1 and FPo1 ZL50019 25 Zarlink Semiconductor Inc. Data Sheet ...
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... When CKOFPO3SEL1-0 = “01,” the output for FPo3 and CKo3 follow the same as Figure 8: Output Timing for CKo1 and FPo1 When CKOFPO3SEL1-0 = “10,” the output for FPo3 and CKo3 follow the same as Figure 9: Output Timing for CKo2 and FPo2 Figure 10 - Output Timing for CKo3 and FPo3 with CK0FPo3SEL1-0=”11” ZL50019 26 Zarlink Semiconductor Inc. ...
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... While there is no frame pulse output directly tied to the CKo4, the output clocks are based on the frame pulse generated by FPo0 FPo5 (FPo_OFF2) FP19EN = 1 CKO5EN = 1 CK5 = 19.44 MHz Figure 12 - Output Timing for CKo5 and FPo5 (FPo_OFF2) ZL50019 Figure 11 - Output Timing for CKo4 27 Zarlink Semiconductor Inc. Data Sheet ...
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... Bit Delay = 1 Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. Figure 13 - Input Bit Delay Timing Diagram (ST-BUS) ZL50019 Channel 0 Channel ...
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... Input Bit Sampling Point Programming In addition to the input bit delay feature, the ZL50019 allows users to change the sampling point of the input bit by programming STIN[n]SMP 1-0 (bits the Stream Input Control Register (SICR0 - 31). For input streams operating at any rate except 16.384 Mbps, the default sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position ...
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... Last Channel STio[ Bit Adv = 1 Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. Figure 16 - Output Bit Advancement Timing Diagram (ST-BUS) ZL50019 Channel ...
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... Last Channel STio[n] 1 STo[n]FA1 ( Mbps) Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively. Figure 17 - Output Fractional Bit Advancement Timing Diagram (ST-BUS) ZL50019 Last Channel Fractional Bit Advancement = 1/4 Bit Last Channel ...
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... Control Register (CR) must be set before V/C (bit 14) in the Connection Memory Low when CMM = 0. If the VAREN bit is not set and the device is programmed for variable delay mode, the information read on the output stream will not be valid. ZL50019 HiZ CH2 ...
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... The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay mode. ZL50019 n-m < < n-m < frame - (m-n) ...
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... UAEN (bit 15) in the Connection Memory Low. When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the ZL50019 will operate in one of the special modes described in Table 53 on page 81. When the per-channel message mode is enabled, MSG7 - 0 (bit the Connection Memory Low (CM_L) will be output via the serial data stream as message output data. When the per-channel message mode is enabled, the µ ...
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... Slave mode, output clocks and frame pulses are generated based on CKi and FPi. In Divided Slave mode, output clocks and frame pulses are directly divided from CKi/FPi; therefore, the output clock rate cannot exceed the CKi rate. In Multiplied Slave mode, the output clocks and frame pulses are generated from a clock ZL50019 11 10 ...
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... DPLL will be fully functional, including its capability of reference monitoring. Note that an external oscillator is required whenever the DPLL is used. Table 7, “ZL50019 Operating Modes” on page 36 summarizes the different modes of operation available within the ZL50019. Each Major mode (explained below) has an associated Minor mode that is determined by setting the relevant Input Control pins and Control Register bits (Table 16, “ ...
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... When the internal DPLL module is in the internal reset mode, all registers remain accessible. Note that applying the DPLL reset does not reset the DPLL registers: they preserve the values that they had prior to entering reset. ZL50019 37 Zarlink Semiconductor Inc. ...
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... CKo0 CKo1 CKo2 CKo3 CKo4 CKo5 FPo0 FPo1 FPo2 FPo3 FPo5 ZL50019 8 kHz 1.544 MHz (DS1) 2.048 MHz (E1) 4.096 MHz 8.192 MHz 16.384 MHz 19.44 MHz 4.096 MHz 8.192 MHz 16.384 MHz 4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz 1.544 MHz or 2.048 MHz 19 ...
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... Jitter Performance 15.1 Input Clock Cycle to Cycle Timing Variation Tolerance The ZL50019 has an exceptional cycle to cycle timing variation tolerance of 20 ns. This allows the ZL50019 to synchronize off a low cost DPLL when either Divided Slave mode or Multiplied Slave mode. 15.2 Input Jitter Acceptance The input jitter acceptance is specified in standards as the minimum amount of jitter of a certain frequency on the input clock that the DPLL must accept without making cycle slips or losing lock ...
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... The monitor makes a decision about reference validity after two consecutive measurements with respect to its time base. The time base for multi-period monitoring is 10 seconds. The time base is defined in the number of reference clock cycles. ZL50019 Reference Comment Frequency 8 kHz 10 UIp-p 1 ...
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... Refer to Figure 24 on page 88, Figure 25 on page 89, Figure 26 on page 90 and Figure 27 on page 91 for the microprocessor timing. 18.0 Device Reset and Initialization The RESET pin is used to reset the ZL50019. When this pin is low, the following functions are performed: • synchronously puts the microprocessor port in a reset state • ...
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... Pseudo Random Bit Generation and Error Detection The ZL50019 has one Bit Error Rate (BER) transmitter and one BER receiver for each pair of input and output streams, resulting in 32 transmitters connected to the output streams and 32 receivers associated with the input streams. Each transmitter can generate a BER sequence with a pattern of 2 Each transmitter can start at any location on the stream and will last for a minimum of 1 channel to a maximum of 1 frame time (125 µ ...
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... The input channel and output channel encoding law are configured independently. If the output channel coding is set to be different from the input channel, the ZL50019 performs translation between the two standards. If the input and output encoding laws are set to the same standard, no translation occurs. As the V/D (bit 4) of the Connection Memory High (CM_H) must be set on a per-channel basis not possible to translate between voice and data encoding laws ...
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... Test Access Port (TAP) Controller. 22.1 Test Access Port (TAP) The Test Access Port (TAP) accesses the ZL50019 test functions. It consists of three input pins and one output pin as follows: • Test Clock Input (TCK) - TCK provides the clock for the test logic. TCK does not interfere with any on-chip clock and thus remains independent in the functional mode ...
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... Instruction Register The ZL50019 uses the public instructions defined in the IEEE-1149.1 standard. The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDi when the TAP Controller is in its shifted-OR state. These instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDi and TDo during data register scanning ...
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... R Only Reference Failure Status Register H 006A R/W Reference Mask Register H 006B R Only Reference Frequency Status Register H 006C R/W Output Jitter Control Register H Table 15 - Address Map for Registers (A13 = 0) ZL50019 Register Abbreviation Name CR IMS SRR OCFCR OCFSR FPOFF0 FPOFF1 FPOFF2 IFR BERFR0 BERFR1 BERLR0 ...
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... R/W BER Receiver Control Registers 035F H 0360 - R Only BER Receiver Error Registers 037F H Table 15 - Address Map for Registers (A13 = 0) (continued) ZL50019 Register Abbreviation Name SICR0 - 31 SIQFR0 - 31 SOCR0 - 31 BRSR0 - 31 BRLR0 - 31 BRCR0 - 31 BRER0 - 31 47 Zarlink Semiconductor Inc. Data Sheet Reset By Switch/Hardware ...
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... When SLV_DPLLEN is set in Slave mode, CKo[3:0] and FPo[3:0] are generated from CKi and FPi. CKo[5:4] and FPo[5] are locked to the selected input reference (one of REF[3:0]). In this mode of operation, the DPLL retains its functionality, including the generation of the REF_FAIL[3:0] output signals. See Table 7, “ZL50019 Operating Modes” on page 36 for more details OPM1 - 0 Operation Mode ...
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... Note: Unused output streams are tristated (STio = HiZ, STOHZ = Driven High). Refer to SOCR0 - 31 (bit MS1 - 0 Memory Select Bits These two bits are used to select connection memory low, connection high or data mem- ory for access by CPU: Table 16 - Control Register (CR) Bits (continued) ZL50019 CKi_ FPIN ...
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... Register is set to high and the MBPS bit in this register is set to high, the contents of the bits BPD2 - 0 are loaded into bits the Connection Memory Low. Bits the Connection Memory Low and bits Connection Memory High are zeroed. Table 17 - Internal Mode Selection Register (IMS) Bits ZL50019 ...
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... When this bit is low, the DPLL block is in normal operation. When this bit is high, the DPLL block is in software reset state. Refer to Table 15, “Address Map for Registers (A13 = 0)” on page 46 for details regarding which registers are affected. Table 18 - Software Reset Register (SRR) Bits ZL50019 ...
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... CKo0 and FPo0 Enable When this bit is high, output clock CKo0 and output frame pulse FPo0 are enabled. EN When this bit is low, CKo0 and FPo0 are in high impedance state. Table 19 - Output Clock and Frame Pulse Control Register (OCFCR) Bits ZL50019 ...
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... When this bit is low, the output frame pulse FPo2 has the negative frame pulse format. When this bit is high, the output frame pulse FPo2 has the positive frame pulse format. Table 20 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits ZL50019 10 9 ...
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... When this bit is high, FPo0 starts from frame boundary (as defined by GCI-Bus). Note: In Divided Slave modes, CKo3 - 1 cannot exceed frequency of CKi. Note: CKo[5:4] are available in Master mode or in Slave mode with SLV_DPLLEN set. Table 20 - Output Clock and Frame Pulse Selection Register (OCFSR) Bits (continued) ZL50019 ...
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... The binary value of these bits refers to the channel offset from original frame bound- ary. Permitted channel offset values depend on bits 1-0 of this register FOF[n] FPo_OFF[n] Control bits FOF[n]C 1 Note: [n] denotes output offset frame pulse from Table 21 - FPo_OFF[n] Register (FPo_OFF[n]) Bits ZL50019 FOF[n] FOF[n] FOF[n] FOF[n] FOF[n] OFF7 ...
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... BER Error Flag[n]: If BERF[n] is high, it indicates that BER Receiver Error Register [n] (BRER[n]) is not zero. If BERF[n] is low, it indicates that BER Receiver Error Register [n] (BRER[n]) is zero. Note: [n] denotes input stream from 0 - 15. Table 23 - BER Error Flag Register 0 (BERFR0) Bits - Read Only ZL50019 ...
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... BERL[n] BER Receiver Lock[n] If BERL[n] is high, it indicates that BER Receiver of STi[n] is locked. If BERL[n] is low, it indicates that BER Receiver of STi[n] is not locked. Note: [n] denotes input stream from 0 - 15. Table 25 - BER Receiver Lock Register 0 (BERLR0) Bits - Read Only ZL50019 BER ...
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... When this bit is low, the DPLL module is in the operational state. When this bit is high, the DPLL module is in the power saving mode. Registers are not reset and are still accessible in the power saving mode. Table 27 - DPLL Control Register (DPLLCR) Bits ZL50019 ...
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... R2F2 - 0 Reference 2 Frequency Bits: When the RFRE bit of the DPLLCR register is high, these bits are used to select the REF2 input frequency. When the RFRE bit is low, these bits are ignored. Table 28 - Reference Frequency Register (RFR) Bits ZL50019 R3F1 ...
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... R0F2 - 0 Reference 0 Frequency Bits When the RFRE bit of the DPLLCR register is high, these bits are used to select the REF0 input frequency. When the RFRE bit is low, these bits are ignored. Table 28 - Reference Frequency Register (RFR) Bits (continued) ZL50019 ...
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... CFRL register bits represents the center frequency number (CFN) explained under CFRL register bits explanation. The default value of this register should be changed only if compensation for input oscil- lator (or crystal) frequency offset is required, and SHOULD NOT be changed in any other circumstances. Table 30 - Centre Frequency Register - Upper 10 Bits (CFRU) ZL50019 ...
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... Example: If maximum expected jitter amplitude on 2.048 MHz reference is 10UI (i.e 488 4882 ns) (assuming the jitter frequency where DPLL attenuation is big), the LDT should be programmed to be (4882/15. 642 = 0282 H Table 32 - Lock Detector Threshold Register (LDTR) Bits ZL50019 ...
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... External Read/Write Address: 004B H Reset Value: 0000 Bit Name Unused Reserved In normal functional mode, these bits MUST be set to zero. Table 35 - Reference Change Control Register (RCCR) Bits ZL50019 LDI LDI LDI LDI LDI Description ...
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... PMS2 - 0 Preference Mode Selection Bits These bits select one of the preference modes FDM1 - 0 Force DPLL Mode These bits force the DPLL into one of the valid operation modes. Table 35 - Reference Change Control Register (RCCR) Bits (continued) ZL50019 ...
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... These bits represent the frequency of the selected reference indicated by the reference bits (RES1 - 0) in this register RES1 - 0 Reference Select Indicator Bits: These bits indicate which one of the four reference inputs (REF0 - 3 pins) is being selected by the device. Table 36 - Reference Change Status Register (RCSR) Bits - Read Only ZL50019 ...
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... If any of these bits are set, the interrupt output will become active unless the Interrupt Mask Register (IMR) has a high value for that particular bit. Note 2: Any of these bits can be cleared by setting the appropriate bit in the Interrupt Clear Register. Table 37 - Interrupt Register (IR) Bits - Read Only ZL50019 ...
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... Writing a “1” to any bit in this register will clear the corresponding bit in the Interrupt Register (IR). The Interrupt Clear Register is self-clearing, i.e. once it has completed its action, the ICR register bit returns Unused Reserved In normal functional mode, this bit MUST be set to one. Table 39 - Interrupt Clear Register (ICR) Bits ZL50019 ...
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... Reference 1 Single Period Upper Limit Fail Bit If the device sets this bit to high, the input REF1 fails the single-period upper limit check. (See Table 10, “Values for Single Period Limits” on page 40) Table 40 - Reference Failure Status Register (RSR) Bits - Read Only ZL50019 ...
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... When this bit is high, it masks the single-period lower limit check (or forces pass) for REF3. 12 R3MU Reference 3 Single-period Upper Limit Mask Bit When this bit is high, it masks the single-period upper limit check (or forces pass) for REF3. Table 41 - Reference Mask Register (RMR) Bits ZL50019 ...
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... When this bit is high, it masks the multi-period upper limit check (or forces pass) for REF0. 1 R0ML Reference 0 Single-period Lower Limit Mask Bit When this bit is high, it masks the single-period lower limit check (or forces pass) for REF0. Table 41 - Reference Mask Register (RMR) Bits (continued) ZL50019 ...
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... R3FS 2 Bit Name Unused Reserved. In normal functional mode, these bits are zero R3FS2 - 0 Reference 3 Frequency Status Bits These bits report detected frequency of REF3. Table 42 - Reference Frequency Status Register (RFSR) Bits - Read only ZL50019 MMU ...
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... R1FS2 - 0 Reference 1 Frequency Status Bits: These bits report detected frequency of REF1. R1FS2 R0FS2 - 0 Reference 0 Frequency Status Bits: These bits report detected frequency of REF0. R0FS2 Table 42 - Reference Frequency Status Register (RFSR) Bits - Read only (continued) ZL50019 R3FS R3FS R2FS ...
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... The binary value of these bits refers to the number of bits that the input stream will be delayed relative to FPi. The maximum value is 7. Zero means no delay. Input Data Sampling Point Selection Bits STIN[n]SMP1 - 0 STIN[n]SMP1-0 Table 44 - Stream Input Control Register (SICR0 - 31) Bits ZL50019 ...
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... Bit Name STIN[n]DR3 - 0 Input Data Rate Selection Bits: Note: [n] denotes input stream from 0 - 31. Table 44 - Stream Input Control Register (SICR0 - 31) Bits (continued) ZL50019 STIN[n] STIN[n] STIN[n] STIN[n] STIN[n] BD2 BD1 BD0 SMP1 Description ...
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... These three bits are used to control STi[n]’s quadrant frame 2, which is defined as Ch16 to 23, Ch32 to 47, Ch64 to 95 and Ch128 to 191 for the 2.048 Mbps, 4.096 Mbps 8.192 Mbps, and 16.384 Mbps modes respectively. Table 45 - Stream Input Quadrant Frame Register (SIQFR0 - 31) Bits ZL50019 ...
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... These three bits are used to control STi[n]’s quadrant frame 0, which is defined as Ch0 to 7, Ch0 to 15, Ch0 to 31 and Ch0 to 63 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps modes respectively. Note: [n] denotes input stream from 0 - 31. Table 45 - Stream Input Quadrant Frame Register (SIQFR0 - 31) Bits (continued) ZL50019 ...
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... The binary value of these bits refers to the number of bits that the output stream advanced relative to FPo. The maximum value is 7. Zero means no advancement STO[n]DR3 - 0 Output Data Rate Selection Bits Note: [n] denotes output stream from 0 - 31. Table 46 - Stream Output Control Register (SOCR0 - 31) Bits ZL50019 STOHZ STO[n] ...
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... Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively. The minimum number of BER channels these bits are set to zero, no BER test will be performed. Note: [n] denotes input stream from 0 - 31. Table 48 - BER Receiver Length Register [n] (BRLR[n]) Bits ZL50019 ...
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... The binary value of these bits refers to the bit error counts. When it reaches its maxi- mum value of 0xFFFF, the value will be held and will not rollover. Note: [n] denotes input stream from 0 - 31. Table 50 - BER Receiver Error Register [n] (BRER[n]) Bits - Read Only ZL50019 ...
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... When this bit is low, normal switch without µ-law/A-law conversion. Connec- tion memory high will be ignored. When this bit is high, switch with µ-law/A-law conversion, and connection memory high controls the conversion method. Table 52 - Connection Memory Low (CM_L) Bit Assignment when CMM = 0 ZL50019 A8 Stream [ ...
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... In normal functional mode, these bits MUST be set to zero MSG7 - 0 Message Data Bits 8-bit data for the message mode. Not used in the per-channel tristate and BER test modes. Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 ZL50019 SSA ...
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... If this is high, the connection memory is in the per-channel control mode which is per-channel tristate, per-channel message mode or per-channel BER mode. µ- Note: For proper law/A-law conversion, the CM_H bits should be set before Bit 15 (UAEN bit) is set to high. Table 53 - Connection Memory Low (CM_L) Bit Assignment when CMM = 1 ZL50019 ...
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... Output Coding Law µ- Note 1: For proper law/A-law conversion, the CM_H bits should be set before Bit 15 of CM_L is set to high. Note 2: Refer to G.711 standard for detail information of different laws. Table 54 - Connection Memory High (CM_H) Bit Assignment ZL50019 ...
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... The crystal accuracy only affects the output clock accuracy in the freerun or the holdover mode. The crystal specification is as follows: Frequency Tolerance Oscillation Mode Resonance Mode Load Capacitance ZL50019 OSCi 20 MHz 1 MΩ OSCo Figure 21 - Crystal Oscillator Circuit ...
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... Figure 22 on page 85 buffered version of the 20 MHz input clock connected to the internal circuitry. XC For applications requiring ±32 ppm clock accuracy, the following requirements should be met: Frequency Tolerance Rise and Fall Time Duty Cycle ZL50019 35 Ω +3.3 V OSCi +3 MHz OUT ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * Note 1: Maximum leakage on pins (output or I/O pins in high impedance state) is over an applied voltage ( ZL50019 Symbol V ...
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... Timing Parameter Measurement Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low † Characteristics are over recommended operating conditions unless otherwise stated. ALL SIGNALS Figure 23 - Timing Parameter Measurement Voltage Levels ZL50019 Sym. Level V 0 DD_IO V 0 DD_IO V 0 ...
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... RESET pin is set high. † Characteristics are over recommended operating conditions unless otherwise stated. t CSD CS t DSD DS R/W A0-A13 D0-D15 DTA Figure 24 - Motorola Non-Multiplexed Bus Timing - Read Access ZL50019 Sym. Min. Typ. Max CSD t 15 DSD t 0 CSS ...
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... RESET pin is set high. † Characteristics are over recommended operating conditions unless otherwise stated. t CSD CS t DSD DS R/W A0-A13 D0-D15 DTA Figure 25 - Motorola Non-Multiplexed Bus Timing - Write Access ZL50019 Sym. Min. Typ. Max CSD t 15 DSD t 0 CSS ...
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... A delay of 500 µ (see Section 18.2 on page 42) must be applied before the first microprocessor access is Note 2: performed after the RESET pin is set high. † Characteristics are over recommended operating conditions unless otherwise stated A0-A13 D0-D15 RDY Figure 26 - Intel Non-Multiplexed Bus Timing - Read Access ZL50019 Sym. Min. Typ. Max CSD ...
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... A delay of 500 µ (Section 18.2 on page 42) must be applied before the first microprocessor access is performed Note 2: after the RESET pin is set high. † Characteristics are over recommended operating conditions unless otherwise stated A0-A13 D0-D15 RDY Figure 27 - Intel Non-Multiplexed Bus Timing - Write Access ZL50019 Sym. Min. Typ. Max CSD ...
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... AC Electrical Characteristics - OSCi 20 MHz Input Timing Characteristic 1 Input frequency accuracy 2 Duty cycle 3 Input rise or fall time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ See “Performance Characteristics Notes” on page 112. ZL50019 Sym. Min. t 100 TCKP t 20 TCKH t 20 ...
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... CKi Input Clock Rise/Fall Time 8 CKi Input Clock Cycle to Cycle Variation † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50019 Sym. Min ...
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... FPi t FPIS CKi Input Frame Boundary Figure 29 - Frame Pulse Input and Clock Input Timing Diagram (ST-BUS) FPi t FPIS CKi Input Frame Boundary Figure 30 - Frame Pulse Input and Clock Input Timing Diagram (GCI-Bus) ZL50019 t FPIW t FPIH t CKIP t CKIH t rCKI t FPIW t FPIH t CKIP ...
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... STi0 - 31 Bit0 2.048 Mbps Ch31 STi0 - 31 Bit0 4.096 Mbps Ch63 STi0 - 31 Bit1 Bit0 Ch127 Ch127 8.192 Mbps Input Frame Boundary Figure 31 - ST-BUS Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps ZL50019 Sym. Min. Typ. Max. t SIS2 SIS4 t 5 SIS8 t 5 ...
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... Ch31 STi0 - 31 Bit7 4.096 Mbps Ch63 STi0 - 31 Bit6 Bit7 Bit0 Ch127 Ch127 Ch0 8.192 Mbps Input Frame Boundary Figure 33 - GCI-Bus Input Timing Diagram when Operated at 2 Mbps, 4 Mbps, 8 Mbps ZL50019 t SIS16 t SIH16 Bit6 Bit5 Bit4 Bit3 Ch0 Ch0 Ch0 Ch0 t SIS2 ...
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... FPi CKi (16.384 MHz) STi0 - 31 Bit6 Bit7 Bit0 Ch255 Ch255 Ch0 16.384 Mbps Input Frame Boundary Figure 34 - GCI-Bus Input Timing Diagram when Operated at 16 Mbps ZL50019 t SIS16 t SIH16 Bit1 Bit2 Bit3 Bit4 Ch0 Ch0 Ch0 Ch0 97 Zarlink Semiconductor Inc. Data Sheet ...
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... Mbps Ch63 STio0 - 31 Bit0 8.192 Mbps Ch127 STio0 - 31 Bit2 Bit1 Bit0 Ch255 Ch255 Ch255 16.384 Mbps Output Frame Boundary Figure 35 - ST-BUS Output Timing Diagram when Operated Mbps ZL50019 Sym. Min. Typ. Max SOD2 SOD4 ...
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... Ch0 t SOD16 STio0 - 31 Bit5 Bit6 Bit7 Bit0 Ch255 Ch255 Ch255 Ch0 16.384 Mbps Output Frame Boundary Figure 36 - GCI-Bus Output Timing Diagram when Operated Mbps ZL50019 t SOD2 Bit0 Ch0 t SOD4 Bit0 Bit1 Ch0 Ch0 SOD8 Bit1 Bit2 Bit3 Bit4 ...
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... pF; high impedance is measured by pulling to the appropriate rail with the time taken to discharge FPo0 CKo0 STio STio Figure 37 - Serial Output and External Control ODE t ZD_ODE STio HiZ ZL50019 Sym. Min. Typ ZD_ODE t ...
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... Characteristics are over recommended operating conditions unless otherwise stated. FPi CKi (16.384 MHz) FPi CKi (8.192 MHz) FPi CKi (4.096 MHz) Input Frame Boundary FPo0 CKo0 (4.096 MHz) Figure 39 - Input and Output Frame Boundary Offset ZL50019 Sym. Min. Typ. Max FBOS FBOS t FBOS Output Frame Boundary 101 Zarlink Semiconductor Inc ...
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... CKo0 Output Low Time 7 CKo0 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50019 t FPW0 t t FODF0 ...
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... CKo1 Output Low Time 7 CKo1 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50019 t FPW1 t t FODF1 ...
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... CKo2 Output Low Time 7 CKo2 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50019 t FPW2 t t FODF2 ...
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... CKo3 Output Low Time 7 CKo3 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50019 t FPW3 t t FODF3 ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. FPo5 (shares output pin with FPo_OFF2) CKo5 Output Frame Boundary Figure 45 - CKo5 Timing Diagram (19.44 MHz) ZL50019 t CKP4 t t CKH4 CKL4 t fCK4 Sym ...
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... CKo5 Output Low Time 7 CKo5 Output Rise/Fall Time † Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. ZL50019 Sym. Min. Typ. t ...
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... REF @ 8 kHz, 2.048, 4.096, 8.192, 16.384 MHz REF @ 1.544 MHz REF @ 19.44 MHz † Characteristics are over recommended operating conditions unless otherwise stated. ‡ See “Performance Characteristics Notes” on page 112. REF0-3 FPo[n] CKo[n] Figure 46 - REF0 - 3 Reference Input/Output Timing ZL50019 Sym. Min RPMIN ...
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... CKo0 to CKo1 (8.192 MHz) delay 2 CKo0 to CKo2 (16.384 MHz) delay 3 CKo0 to CKo3 (32.768 MHz/16.384 MHz/8.192 MHz/4.096 MHz) delay † Characteristics are over recommended operating conditions unless otherwise stated. ‡ See “Performance Characteristics Notes” on page 112. ZL50019 Sym. Min. t C1D t C2D t ...
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... FPo0 CKo0 (4.096 MHz) CKo4 (1.544 MHz) CKo1 (8.192 MHz) CKo2 (16.384 MHz) CKo5 (19.44 MHz) CKo3 (32.768 MHz) Figure 47 - Output Timing (ST-BUS Format) ZL50019 t C4D t C1D t C2D t C5D t C3D 110 Zarlink Semiconductor Inc. Data Sheet ...
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... Characteristics are over recommended operating conditions unless otherwise stated. ‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. * See “Performance Characteristics Notes” on page 112 ZL50019 † - Accuracy & Switching Min ...
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... Multi-period near limits and far limits are programmed to +/-64.713 ppm & +/-82.487 ppm respectively. (ST4_LIM = 1) 13. Multi-period near limits and far limits are programmed to +/-240 ppm & +/-250 ppm respectively. (ST4_LIM = 0) 14 load on output pin. ZL50019 at 3.3 V and are for design aid only: not guaranteed and not subject to production DD_IO ...
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Zarlink Semiconductor 2003 All rights reserved. 1 ISSUE 214440 ACN 26June03 DATE APPRD. Package Code Previous package codes ...
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Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...