ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 40

• Manufacturer Part Number: ZL50019
• Description: Enhanced 2 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

16.3
Besides total phase change, standards also require a certain rate of the phase change of the output clock. The
phase alignment speed is programmable by the user through a value in the Slew Rate Limit Register (SRLR) as
described in Table 34 on page 63. Stratum 4E requires that the phase alignment speed not exceed 81 ns per
1.326 ms (61ppm). The width of the register and the limiter circuitry provide a maximum phase change alignment
speed of 186 ppm. The phase alignment speed default value is 56 ppm.
16.4
The quality of the four input reference clocks is continuously monitored by the reference monitors. There are
separate reference monitor circuits for the four DPLL references. References are checked for short phase (single
period) deviations as well as for frequency (multi-period) deviations with hysteresis.
The Reference Status Register (RSR) reports the status of the reference monitors. The register bits are described
in Table 40 on page 68. The Reference Mask Register (RMR) allows users to ignore the monitoring features of the
reference monitors. See Table 41 on page 69 for details.
16.5
Values for short phase deviations (upper and lower limit) are programmable through registers. The unit of the binary
values of these numbers is 100 MHz clock period (10 ns). Single period deviation limits are more relaxed than multi
period limits, and are used for early detection of the reference loss, or huge phase jumps.
The values for the upper and lower limits are shown in the following table:
16.6
To monitor reference failure based on frequency offset, multi period checking is performed. Reference validation
time is prescribed by Telcordia GR-1244-CORE and is between 10 and 30 seconds. To meet the criteria for
reference validation time, the time base for multi period monitoring has to be big enough. To implement hysteresis,
the upper limits are split into near upper and far upper limits and the lower limits are split into near lower and far
lower limits. The reference failure is detectable only when the reference passes far limits, but passing is not
detected until the reference is within near limits. The zone between near and far limits, called the “grey zone”, is
required by standards and prevents unnecessary reference switching when the selected reference is close to the
boundary of failure.
The monitor makes a decision about reference validity after two consecutive measurements with respect to its time
base. The time base for multi-period monitoring is 10 seconds. The time base is defined in the number of reference
clock cycles.
Phase Alignment Speed (Phase Slope)
Reference Monitoring
Single Period Reference Monitoring
Multiple Period Reference Monitoring
Table 10 - Values for Single Period Limits
8 kHz
1.544 MHz
2.048 MHz
4.096 MHz
8.192 MHz
16.384 MHz
19.44 MHz
Frequency
Reference
Zarlink Semiconductor Inc.
ZL50019
40
Comment
0.3 UIp-p
0.2 UIp-p
0.2 UIp-p
0.2 UIp-p
0.2 UIp-p
0.2 UIp-p
10 UIp-p
Data Sheet