ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 38

• Manufacturer Part Number: ZL50019
• Description: Enhanced 2 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.0
14.1
The DPLL is capable of synchronizing to one of the following input frequencies:
14.2
The input frequencies of REF 0 - 3 can be automatically detected or programmed independently by the Reference
Frequency Register (RFR) if RFRE (bit 1) in the DPLL Control Register (DPLLCR) is set. The detected frequency of
the selected reference is indicated in the Reference Change Status Register (RCSR). In addition, the detected
frequencies of all four references are indicated in the Reference Frequency Status Register (RFSR). See Table 27
on page 58, Table 28 on page 59, Table 36 on page 65 and Table 42 on page 71 for the detailed bit description of
the DPLL Control Register (DPLLCR), Reference Frequency Register (RFR), Reference Change Status Register
(RCSR) and Reference Frequency Status Register (RFSR), respectively.
14.3
The DPLL generates a limited number of output signals. All signals are synchronous to each other and in the
normal operating mode, are locked to the selected input reference. The DPLL provides outputs with the following
frequencies:
Input Frequencies
Input Frequencies Selection
Output Frequencies
DPLL Frequency Behaviour
CKo0
CKo1
CKo2
CKo3
CKo4
CKo5
FPo0
FPo1
FPo2
FPo3
FPo5
Table 8 - DPLL Input Reference Frequencies
4.096 MHz
8.192 MHz
16.384 MHz
4.096 MHz, 8.192 MHz, 16.384 MHz or 32.768 MHz
1.544 MHz or 2.048 MHz
19.44 MHz
8 kHz (244 ns wide pulse)
8 kHz (122 ns wide pulse)
8 kHz (61 ns wide pulse)
8 kHz (244 ns, 122 ns, 61 ns or 30 ns wide pulse)
8 kHz (51 ns wide pulse)
Table 9 - Generated Output Frequencies
Zarlink Semiconductor Inc.
1.544 MHz (DS1)
2.048 MHz (E1)
ZL50019
16.384 MHz
4.096 MHz
8.192 MHz
19.44 MHz
8 kHz
38
Data Sheet