ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 64

• Manufacturer Part Number: ZL50019
• Description: Enhanced 2 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

External Read/Write Address: 004B
Reset Value: 0000
6 - 5
4 - 2
1 - 0
Bit
15
7
0
14
0
PMS2 - 0
FDM1 - 0
PRS1 - 0
Name
MTR
H
13
Table 35 - Reference Change Control Register (RCCR) Bits (continued)
0
MTIE Reset
When this bit is low, the MTIE circuit applies a phase offset between the reference input
clock and the DPLL output clock and the phase offset value is maintained. When this bit
is high, MTIE circuit is in its reset state and the phase offset value is reset to zero,
causing alignment of the DPLL output clocks to nearest edge of the selected input
reference.
Preferred Reference Selection Bits
These bits select the preferred reference from one of the input references.
Preference Mode Selection Bits
These bits select one of the preference modes:
Force DPLL Mode
These bits force the DPLL into one of the valid operation modes.
12
0
H
11
0
PMS2
10
0
0
0
0
1
1
0
PRS1
FDM1
0
0
1
1
0
0
1
1
110 - 111
9
0
Zarlink Semiconductor Inc.
PMS1
0
0
1
1
0
0
ZL50019
PRS0
FDM0
8
0
0
1
0
1
0
1
0
1
64
PMS0
MTR
7
0
1
0
1
0
1
Description
Preferred Reference Selection
PRS
6
1
Operation Mode
Preference as per the setting
Automatic
Holdover
Freerun
Normal
of the PRS1 - 0 bits
PRS
Preference Mode
5
0
REF0
REF1
REF2
REF3
No Preference
Force REF0
Force REF1
Force REF2
Force REF3
Reserved
PMS
4
2
PMS
3
1
PMS
2
0
Data Sheet
FDM
1
1
FDM
0
0