ZL50019 ZARLINK [Zarlink Semiconductor Inc], ZL50019 Datasheet - Page 37

• Manufacturer Part Number: ZL50019
• Description: Enhanced 2 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

12.3
When the device is in Multiplied Slave mode, device hardware is used to multiply CKi internally. STio0 - 31 are
driven by this internally generated clock. In this mode, the output data rate can be any specified data rate, but the
output streams and clocks may have different jitter characteristics from the input clock (CKi). If the DPLL is not
enabled, an external oscillator is not required in Multiplied Slave mode.
13.0
The DPLL accepts four input references and delivers six output clocks and five output frame pulses. The DPLL
meets or exceeds all of the requirements of the Telcordia GR-1244-CORE standard for a Stratum 4E compliant
PLL. This includes the freerun, reference switching and monitoring, jitter/wander attenuation and holdover
functions. The intrinsic output jitter of the DPLL does not exceed 1 ns (except for the 1.544 MHz output).
The DPLL is able to lock to an input reference presented on the REF0 - 3 inputs. It is possible to force the DPLL
module to lock to a selected reference, to prefer one reference, to enter holdover mode or to freerun.
13.1
There are four functional modes for the DPLL: normal, holdover, automatic and freerun modes. In addition to these
four functional modes, the DPLL can also be programmed to internal reset mode.
13.1.1
In the normal operating mode, the DPLL generates clocks and frame pulses that are phase locked to the active
input reference. Jitter on the input clock is attenuated by the DPLL.
13.1.2
In holdover mode, the DPLL no longer synchronizes the output clock to any input reference. It maintains the
frequency that it was at prior to entering holdover mode. The holdover operation typically happens when the input
clock becomes unreliable or is lost altogether. It takes some time for the system to realize that the input clock is
unreliable. Meanwhile, the DPLL tracks an unreliable clock. Therefore the DPLL could hold to an invalid frequency
when it enters holdover mode. In order to prevent this situation, the DPLL stores the current frequency at regular
intervals in holdover memory so that it can restore the frequency of the input clock just after the input clock became
unreliable.
13.1.3
In this mode, the state machine controls the DPLL based on the settings in the registers and the quality of the
reference input clocks. The DPLL is internally either in normal or in holdover mode.
13.1.4
In freerun mode, the DPLL generates a fixed output frequency based on the crystal oscillator frequency. To meet
Stratum 4E, the accuracy of the circuitry for the freerunning output clock must be 32 ppm or better.
13.1.5
DPLL_IRM (bit 0) in the DPLL Control Register (DPLLCR) enables the internal reset mode. In the internal reset
mode, the DPLL module is disabled to save power. The circuit will be reset continuously and no output clocks will
be generated. When the internal DPLL module is in the internal reset mode, all registers remain accessible. Note
that applying the DPLL reset does not reset the DPLL registers: they preserve the values that they had prior to
entering reset.
Multiplied Slave Mode Performance
DPLL Functional Modes
Overall Operation of the DPLL
Normal Operating Mode
Holdover Mode
Automatic Mode
Freerun Mode
DPLL Internal Reset Mode
Zarlink Semiconductor Inc.
ZL50019
37
Data Sheet