ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet
ZL50050GAC
Related parts for ZL50050GAC
ZL50050GAC Summary of contents
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... K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion ( 16 Mbps), and 32 Inputs and 32 Outputs Ordering Information ZL50050GAC ZL50050GAG2 196 Ball PBGA** Trays *Pb Free Tin/Silver/Copper 4.096 Mbps, 8.192 Mbps or 16.384 Mbps in any combination fixed allocation of 8 input and 8 output streams at 32.768 Mbps • ...
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High impedance-control outputs for external drivers on Local and Backplane ports • Per-channel message mode for Local and Backplane output streams • Connection memory block programming for fast device initialization • BER testing for Local and Backplane ports. • ...
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Device Overview The ZL50050 has two data ports, the Backplane and the Local port. Both the Backplane and Local ports have two independent modes of operation, either 16 input and 16 output streams operated at 2.048 Mbps, 4.096 Mbps, 8.192 ...
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Unidirectional and Bi-directional Switching Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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The Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - ZL50050 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Per-stream Input and Output Data Rate Selection: Backplane and Local, Non-32 Mbps Mode and 32 Mbps Mode . . . . . . . . . . . . . . . . . . . . ...
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Table 49 - Local Output Bit Rate (LOBR) Programming Table ...
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Pinout Diagram: (as viewed through top of package) A1 corner identified by metallized marking, mold indent, ink dot, or right-angled corner BSTo1 BSTo2 BSTo5 BSTo0 C IC_GND BSTo7 BSTo8 D IC_GND BSTo6 BSTo10 E ...
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Pin Description ZL50050 Package Pin Name Coordinates (196-ball PBGA) Device Timing C8i P10 FP8i M10 C8o N10 FP8o N11 C16o M9 FP16o P12 ZL50050 Description Master Clock (5 V Tolerant Schmitt-Triggered Input). This pin accepts an 8.192 MHz clock. The ...
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Pin Description (continued) ZL50050 Package Pin Name Coordinates (196-ball PBGA) Backplane and Local Inputs BSTi0-7 G1, H1, H2, H3, J1, J2, K1, J3 BSTi8-15 L1, K2, M1, L2, N1, K3, L3, M2 LSTi0-7 K14, J13, J14, K13, M14, J12, L14, ...
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Pin Description (continued) ZL50050 Package Pin Name Coordinates (196-ball PBGA) LSTi8-15 L13, N14, M12, N12, N13, M11, L12, K12 Backplane and Local Outputs and Control ODE B9 BORS G2 ZL50050 Description Local Serial Input Streams ...
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Pin Description (continued) ZL50050 Package Pin Name Coordinates (196-ball PBGA) BSTo0-7 B3, A1, A2, C4, C5, B2, D2, C2 BSTo8-15 C3, F1, D3, E2, E1, E3, F2, F3 BCSTo0-1 A13, C10 ZL50050 Description Backplane Serial Output Streams ...
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Pin Description (continued) ZL50050 Package Pin Name Coordinates (196-ball PBGA) LORS H13 LSTo0-7 B13, B14, D14, C14, D12, E14, D13, E13 LSTo8-15 E12, F14, G14, G12, F12, F13, H14, G13 ZL50050 Description Local Output Reset State (5 V Tolerant Input ...
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Pin Description (continued) ZL50050 Package Pin Name Coordinates (196-ball PBGA) LCSTo0-1 C12, B12 Microprocessor Port Signals A0 - A14 B1, B4, B5, D5, A3, A4, C6, B6, A5, A6, C7, B7, A7, A8 D15 N7, P7, P6, ...
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Pin Description (continued) ZL50050 Package Pin Name Coordinates (196-ball PBGA) RESET C9 JTAG Control Signals TCK B11 TMS A11 TDi B10 TDo A12 TRST A14 Power and Ground Pins V D6, D7, D8, DD_IO D10, E4, E11, F4, F11, G4, ...
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Pin Description (continued) ZL50050 Package Pin Name Coordinates (196-ball PBGA) V (GND) D4, D11, E5, SS E10, F6, F7, F8, F9, G6, G7, G8, G9, H6, H7, H8, H9, J6, J7, J8, J9, K5, K10, L4, L11, P1, P13, P14 ...
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Unidirectional and Bi-directional Switching Applications The ZL50050 has a maximum capacity of 8,192 input channels and 8,192 output channels. This is calculated from the maximum number of streams and channels: 32 input streams (16 Backplane, 16 Local) at 16.384 ...
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The modes in which one port operates in 32 Mbps Mode while the other port operates in Non-32 Mbps Mode allow data rate conversion between 32.768 Mbps and 16.384 Mbps without loss to the switching capacity. 1.1 Flexible Configuration The ...
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Functional Description 2.1 Switching Configuration The device supports five switching configurations: (1) Unidirectional switch, (2) Backplane-to-Local, (3) Local-to-Backplane, (4) Backplane-to-Backplane, and (5) Local-to-Local. The following sections describe the switching paths in detail. Configurations (2) - (5) enable a non-blocking ...
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Stream Numbers Local Input streams - LSTi0-7 Local Input streams - LSTi8-15 Backplane Input streams - BSTi0-7 Backplane Input streams - BSTi8-15 Local Output streams - LSTo0-7 Local Output streams - LSTo8-15 Backplane Output streams - BSTo0-7 Backplane Output streams ...
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Local Output Port The output traffic on the Local streams are aligned based on the FP8o and C8o output timing signals. Operation of stream data in Connection Mode or Message Mode is determined by the state of the LMM ...
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Frame Pulse Input and Master Input Clock Timing The input frame pulse (FP8i kHz input signal active for 122 ns or 244 ns at the frame boundary. The FPW bit in the Control Register must be ...
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FP8i (ST-BUS) (8 kHz) C8i (ST-BUS) (8.192 MHz) FP8i (GCI-Bus) (8 kHz) C8i (GCI-Bus) (8.192 MHz) Channel 0 BSTi/LSTi0 (32 Mbps) ST-BUS Channel 0 BSTi/LSTi0 ...
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Input Frame Pulse and Generated Frame Pulse Alignment The ZL50050 accepts a frame pulse (FP8i) and generates two frame pulse outputs, FP8o and FP16o, which are aligned to the master frame pulse. There is a constant throughput delay for ...
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There are, however, some cases where data experience more delay than the timing signals. A common example is when multiple data lines are tied together to form bidirectional buses. The large bus loading may cause data to be ...
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Input Channel Delay Programming (Backplane and Local Input Streams) By programming the Backplane or Local Input Channel Delay Registers (BCDR0 - BCDR15 and LCDR0 - LCDR15), users can individually assign the Ch0 position of each input stream to be ...
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SMPL_MODE = LOW FP8i C8i Ch255 BSTi/LSTi0- Bit Delay = 0 (Default) Ch255 BSTi/LSTi0-15 Bit Delay = 1 Ch255 BSTi/LSTi0- Bit Delay = 1/2 Ch255 BSTi/LSTi0-15 Bit Delay = 3/4 3 Ch255 BSTi/LSTi0-15 3 ...
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SMPL_MODE = LOW FP8i C8i BSTi/LSTi0-15 1 BID[4:0]/LID[4:0] = 00000 B Bit delay = 0 bit (Default) BSTi/LSTi0-15 BID[4:0]/LID[4:0] = 00011 B Bit Delay = 3/4 bit SMPL_MODE = HIGH FP8i C8i BSTi/LSTi0-15 1 BID[4:0]/LID[4:0] = 00000 B 3/4 sampling ...
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FP8o System Clock 131.072 MHz BSTo/LSTo0-15 Bit 1 Bit Advancement = 0 (Default) BSTo/LSTo0-15 Bit 1 Bit Advancement = -2 BSTo/LSTo0-15 Bit Advancement = -4 Bit 1 Ch255 BSTo/LSTo0-15 Bit 1 Bit Advancement = -6 Figure 11 - Local and ...
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RESET ODE (input pin) (input pin) Register bit Table 2 - Local and Backplane Output Enable Control Priority (continued) 4.1 LORS/BORS Asserted LOW, Non-32Mbps Mode The data (channel control bit) transmitted by L/BCSTo0-1 replicates the Local/Backplane ...
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Allocated Stream No. C16o L/BCSTo0 L/BCSTo1 1 Period 3-1 2039 0 1 3-3 2040 2 3 2041 4 5 2042 6 7 2043 8 9 2044 10 11 2045 12 13 3-2 3-2 2046 14 15 2047 0 1 3-3 ...
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Allocated Stream No. C16o L/BCSTo0 L/BCSTo1 1 Period 2036 10 2037 12 2038 14 3-1 2039 0 3-3 2040 2 2041 4 2042 6 2043 8 2044 10 2045 12 3-2 2046 14 2047 0 3-3 2048 ...
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Figure 12, Local/Backplane Port External High-Impedance Control Bit Timing (Non-32 Mbps Mode) shows the channel control bits for L/BCSTo0 and L/BCSTo1 in one possible scenario which includes stream L/BSTo0 at a data rate of 16.384 Mbps, L/BSTo1 at 8.192 Mbps, ...
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LORS/BORS Asserted LOW, 32 Mbps Mode Note that when the devices are operating in Local or Backplane 32 Mbps mode, some of the output streams (the upper half of the available streams) are unused. The LE/BE bits of the ...
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Allocated Stream No. C16o L/BCSTo0 1 Period 3-1 2039 0 2040 2 2041 4 3-2 2042 6 2043 0 2044 2 2045 4 2046 6 2047 0 2048 ...
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Allocated Stream No. C16o L/BCSTo0 1 Period 2035 0 3-3 2036 2 2037 4 2038 6 3-1 2039 0 2040 2 2041 4 3-2 2042 6 2043 0 2044 2 2045 4 2046 6 2047 0 2048 ...
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Figure 13, Local and Backplane Port External High-Impedance Control Timing (32 Mbps Mode) shows the channel control bits for L/BCSTo0 and L/BCSTo1. FP8o C8o L/BSTo0 Channel 0 bits 7-0 (32 Mbps) L/BSTo1 Channel 0 (32 Mbps) bits 7-0 L/BSTo2 Channel ...
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Data Delay Through the Switching Paths Serial data which goes into the device is converted into parallel format and written to consecutive locations in the data memory. Each data memory location corresponds to the input stream and channel number. ...
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By default, when the input channel delay, Assuming that m (input channel) and n (output channel) are equal, we have the figure below, in which the delay between the input data being written and the output data being read is ...
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When the input channel delay is enabled, the data throughput delay is frames - α n). Assuming that m (input channel) and n (output channel) are equal, we have the figure below, in which ...
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Bit Error Rate Test Independent Bit Error Rate (BER) testers are provided for the Local and Backplane ports. In both ports there is a BER transmitter and a BER receiver. The transmitter and receiver are each independently controlled to ...
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BE) of the respective connection memories should be set to HIGH to enable the outputs for the selected channels. The BER receive channel numbering is not affected by the input channel delay value. It means that the BER receive ...
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Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer to Section 9.3, Connection Memory Block Programming. 5. Set ODE pin to HIGH after the connection memories are programmed to ensure that bus contention ...
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Backplane Connection Memory The Backplane Connection Memory (BCM 16-bit wide memory with 4,096 memory locations to support the Backplane output port. The most significant bit of each word, bit[15], selects the source stream from either the Backplane ...
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The Backplane Block Programming data bits, BBPD[2:0], of the Block Programming Register, will be loaded into bits[15:13] respectively, of the Backplane Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 10 BBPD2 ...
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Test Data Output (TDo) Depending on the previously applied sequence to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDo. The data out of the TDo is clocked ...
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Memory Address Mappings When the most significant bit, A14, of the address bus is set to’1’, the microprocessor performs an access to one of the device’s internal memories. The Control Register bits MS[2:0] indicate which memory (Local Connection, Local ...
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Backplane Data Memory Bit Definition The 8-bit Backplane Data Memory (BDM) has 4,096 positions. The locations are associated with the Backplane input streams and channels. As explained previously, address bits A13-A0 of the microprocessor define the addresses of the ...
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Bit Name 12:8 LSAB[4:0] Source Stream Address Bits The binary value of these 5 bits represents the input stream number. Ignored when LMM is set HIGH. 7:0 LCAB[7:0] Source Channel Address Bits / Message Mode Data The binary value of ...
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Bit Name 15 BSRC Backplane Source Control Bit When LOW, the source is from the Local input port (Local Data Memory). When HIGH, the source is from the Backplane input port (Backplane Data Memory). Ignored when BMM is set HIGH. ...
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Bit Name 8:0 BCAB[8:0] Source Channel Address Bits / Message Mode Data The binary value of these 9 bits represents the input channel number, when BMM is LOW. Bits BCAB[7:0] transmitted as data when BMM is set HIGH. Note: When ...
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A14-A0 010D - 011C Backplane Input Bit Rate Register 0 - 15, BIBRR0 - 012D - 013C Backplane Output Bit Rate Register 0 - 15, BOBRR0 - 014D Memory BIST Register, MBISTR H 3FFF ...
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Reset Bit Name Value 8 FPW 0 Frame Pulse Width When LOW, the user must apply a 122 ns frame pulse on FP8i; the FP8o pin will output a 122 ns wide frame pulse; FP16o will output a 61ns wide ...
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ZL50050 (a) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (b) Frame Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL) = ...
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Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i (f) Pulse Width = 122 ns, Control Register Bit8 (FPW Control Register Bit6 (C8IPOL C8i FP8i ...
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Block Programming Register (BPR) Address 0001 . H The Block Programming Register stores the bit patterns to be loaded into the connection memories when the Memory Block Programming feature is enabled. The BPE, LBPD[2:0] and BBPD[2:0] bits in the ...
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Bit Error Rate Test Control Register (BERCR) Address 0002 . H The BER Test Control Register controls Backplane and Local port BER testing. It independently enables and disables transmission and reception configured as follows: Reset Bit Name ...
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Reset Bit Name Value 2 SBERRXL 0 Start Bit Error Rate Receiver for Local A LOW to HIGH transition enables the Local BER receiver. The receiver monitors incoming data for reception of the seed value. When detected, the LOCK state ...
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Local Channel Delay Bits 8-0 (LCD8 - LCD0) These nine bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data from the Local input pins. The input channel delay can be selected ...
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Local Input Bit Delay Registers (LIDR0 to LIDR15) Addresses 0023 to 0032 . H H There are sixteen Local Input Delay Registers (LIDR0 to LIDR15). When the SMPL_MODE bit in the Control Register is LOW, the input data sampling ...
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LIDn LID4 LID3 LID2 LID1 ...
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Backplane Input Channel Delay Registers (BCDR0 to BCDR15) Addresses 0043 to 0052 H H Sixteen Backplane Input Channel Delay Registers (BCDR0 to BCDR15) allow users to program the input channel delay for the Backplane input data streams BSTi0-15. The ...
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Backplane Input Bit Delay Registers (BIDR0 to BIDR15) Addresses 0063 to 0072 H H There are sixteen Backplane Input Delay Registers (BIDR0 to BIDR15). When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point ...
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Backplane Input Delay Bits 4-0 (BID[4:0]) When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to sample each input. Input bit delay adjustment can range period. ...
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BIDn BID4 BID3 BID2 Table 29 - Backplane Input Bit Delay and Sampling Point Programming Table (continued) 14.8 Local Output Advancement Registers (LOAR0 to LOAR15) ...
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Local Output Advancement For 2 Mbps, 4 Mbps, 8 Mbps & 16 Mbps Clock Rate 131.072 MHz -4 cycles (~31 ns) -6 cycles (~46 ns) Table 31 - Local Output Advancement (LOAR) Programming Table (continued) 14.9 Backplane Output Advancement Registers ...
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Local Bit Error Rate (BER) Registers 14.10.1 Local BER Start Send Register (LBSSR) Address 00C3 . H The Local BER Start Send Register defines the output channel and the stream on which the BER sequence starts to be transmitted. ...
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Local Transmit BER Length Register (LTXBLR) Address 00C4 . H Local BER Transmit Length Register (LTXBLR) defines how many channels of the BER sequence will be transmitted during each frame. The minimum length of the BER transmitter is 1 ...
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Local BER Start Receive Register (LBSRR) Address 00C6 . H Local BER Start Receive Register defines the input stream and start channel at which the BER sequence shall start to be received. The LBSRR register is configured differently for ...
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Backplane Bit Error Rate (BER) Registers 14.11.1 Backplane BER Start Send Register (BBSSR) Address 00C8 . H Backplane BER Start Send Register defines the output channel and the stream on which the BER sequence is transmitted. The minimum length ...
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Backplane Receive BER Length Register (BRXBLR) Address 00CA . H Backplane Receive BER Length Register (BRXBLR) defines how many channels of the BER sequence will be received in each frame. The BRXBLR register is configured as follows: Reset Bit ...
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Backplane BER Count Register (BBCR) Address 00CC . H Backplane BER Count Register contains the number of counted errors. This register is read-only. The BBCR register is configured as follows: Reset Bit Name Value 15:0 BBC[15:0] 0 Table 45 ...
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Local Output Bit Rate Registers (LOBRR0 - LOBRR15) Addresses 00ED to 00FC . H H Sixteen Local Output Bit Rate Registers allow the bit rate for each individual stream to be set Mbps. ...
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MODE32B Table 51 - Backplane Input Bit Rate (BIBR) Programming Table 14.13.2 Backplane Output Bit Rate Registers (BOBRR0 - BOBRR15) Addresses 012D to 013C . H H Sixteen Backplane Output Bit Rate Registers allow the ...
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Memory BIST Register Address 014D . H The Memory BIST Register enables the self-test of chip memory. Two consecutive write operations are required to start MBIST: the first with only bit 12 (LV_TM) set HIGH (i.e., 1000h); the second ...
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Reset Bit Name Value 2 BISTSCL 0 Local Connection Memory Start BIST Sequence Sequence enabled on LOW to HIGH transition. 1 BISTCCL 0 Local Connection Memory BIST Sequence Completed (Read-only) This bit must be polled - when HIGH, indicates completion ...
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DC Electrical Characteristics Absolute Maximum Ratings* Parameter 1 Core Supply Voltage 2 I/O Supply Voltage 3 PLL Supply Voltage 4 Input Voltage (non-5 V tolerant inputs) 5 Input Voltage (5 V tolerant inputs) 6 Continuous Current at digital outputs ...
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DC Electrical Parameters Characteristics 1a Supply Current I 1b Supply Current Supply Current U 1d Supply Current T 2 Input High Voltage S 3 Input Low Voltage 4 Input Leakage (input pins) Input Leakage (bi-directional pins) Weak ...
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AC Electrical Characteristics AC Electrical Characteristics Timing Parameter Measurement: Voltage Levels Characteristics 1 CMOS Threshold 2 Rise/Fall Threshold Voltage High 3 Rise/Fall Threshold Voltage Low Input and Output Clock Timing Characteristic 1 FP8i, Input Frame Pulse Width 2 Input ...
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Input and Output Clock Timing (continued) Characteristic 13 C8o Clock Period 14 C8o Clock Pulse Width High 15 C8o Clock Pulse Width Low 16 C8o Clock Rise/Fall Time 17 FP16o Frame Pulse Width 18 FP16o Output Delay (from frame pulse ...
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FP8i (244 ns) t IFPS244 FP8i (122 ns) t ICL C8i CK_int * FP8o (244 ns) t FPFBF8_244 FP8o (122 ns) t OCL8 C8o FP16o (122 ns) FP16o (61ns) t FPFB16_61 t t OCL16 OCH16 C16o Note *: CK_int is ...
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FP8i (244 ns) FP8i (122 ns) t ICL C8i CK_int * FP8o (244 ns) FP8o (122 ns) t OCL8 C8o FP16o (122 ns) FP16o (61 ns) t FPFB16_61 t t OCH16 OCL16 C16o Note *: CK_int is the internal clock ...
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Local and Backplane Data Timing Characteristic 1 Local/Backplane Input Data Sampling Point 2 Local/Backplane Serial Input Set-up Time 3 Local/Backplane Serial Input Hold Time 4 Output Frame Boundary Offset 5 Local/Backplane Serial Output Delay ZL50050 Sym. Min. Typ. Max. t ...
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FP8i C8i CK_int * L/BSTi0-15 8.192 Mbps 1 0 L/BSTi0-15 Bit0 4.096 Mbps Ch63 L/BSTi0-15 Bit0 2.048 Mbps Ch31 FP8o C8o CK_int * L/BSTo0-15 Bit1 Bit0 8.192 Mbps Ch127 Ch127 L/BSTo0-15 Bit0 4.096 Mbps Ch63 L/BSTo0-15 Bit0 2.048 Mbps Ch31 ...
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FP8i C8i CK_int * L/BSTi0 32.768 Mbps L/BSTi0-15 Bit1 16.384 Mbps Ch255 FP8o C8o CK_int * L/BSTo0-7 Bit1 Bit1 32.768 Mbps Ch511 Ch511 L/BSTo0-15 16.384 Mbps Note *: CK_int is the internal clock signal of 131.072 MHz Figure ...
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FP8i C8i CK_int * L/BSTi0- 8.192 Mbps L/BSTi0-15 Bit7 Ch63 4.096 Mbps Bit7 L/BSTi0-15 Ch31 2.048 Mbps FP8o C8o CK_int * L/BSTo0-15 Bit6 Bit7 Ch127 Ch127 8.192 Mbps L/BSTo0-15 Bit7 Ch63 4.096 Mbps L/BSTo0-15 Bit7 2.048 Mbps Ch31 ...
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FP8i C8i CK_int * L/BSTi0 32.768 Mbps L/BSTi0-15 Bit6 Bit7 16.384 Mbps Ch255 Ch255 FP8o C8o CK_int * L/BSTo0-7 Bit5 Bit6 32.768 Mbps Ch511 Ch511 L/BSTo0-15 Bit7 Ch255 16.384 Mbps Note *: CK_int is the internal clock signal ...
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Local and Backplane Output High-Impedance Timing Characteristic 1 STo delay - Active to High-Z - High-Z to Active 2 Output Driver Enable (ODE) Delay to Active Data Output Driver Enable (ODE) Delay to High-Impedance Note 1: High Impedance is measured ...
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Input Clock Jitter Tolerance Jitter Frequency 1 1 kHz 2 10 kHz 3 50 kHz 4 66 kHz 5 83 kHz 6 95 kHz 7 100 kHz 8 200 kHz 9 300 kHz 10 400 kHz 11 500 kHz 12 ...
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Non-Multiplexed Microprocessor Port Timing Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 Address hold after DS ...
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AC Electrical Characteristics - JTAG Test Port Timing Characteristic 1 TCK Clock Period 2 TCK Clock Pulse Width High 3 TCK Clock Pulse Width Low 4 TMS Set-up Time 5 TMS Hold Time 6 TDi Input Set-up Time 7 ...
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TOP VIEW NOTES:- 1. Controlling dimensions are in MM. 2. Seating plane is defined by the spherical crown of the solder balls. 3. Not to scale. 4. Ball arrangement array c Zarlink Semiconductor 2003 All rights reserved. ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in ...