ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 64

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.7
Addresses 0063
There are sixteen Backplane Input Delay Registers (BIDR0 to BIDR15).
When the SMPL_MODE bit in the Control Register is LOW, the input data sampling point defaults to the 3/4 bit
location and BIDR0 to BIDR15 define the input bit and fractional bit delay of each Backplane stream. The possible
bit delay adjustment is up to 7
When the SMPL_MODE bit is HIGH, BIDR0 to BIDR15 define the input bit sampling point as well as the integer bit
delay of each Backplane stream. The input bit sampling point can be adjusted in 1/4 bit increments. The bit delay
can be adjusted in 1-bit increments from 0 to 7 bits.
The BIDR0 to BIDR15 registers are configured as follows:
Backplane Non-32 Mbps Mode,
n = 0 to 7 for Backplane
(where n = 0 to 15 for
Backplane Input Bit Delay Registers (BIDR0 to BIDR15)
32 Mbps Mode)
BIDRn Bit
15:5
4:0
H
to 0072
Table 28 - Backplane Input Bit Delay Register (BIDRn) Bits
H
3
/
4
Reserved
bits, in steps of
BID[4:0]
Name
Reset
Value
Zarlink Semiconductor Inc.
0
0
1
/
4
ZL50050
bit.
Reserved
Must be set to 0 for normal operation
Backplane Input Bit Delay Register
When SMPL_MODE = LOW, the binary value of these
bits refers to the input bit fractional delay value (0 to 7
When SMPL_MODE = HIGH, the binary value of BID[1:0]
refers to the input bit sampling point (
refers to the integer bit delay value (0 to 7 bits).
64
Description
1
/
4
to
4
/
4
Data Sheet
). BID[4:2]
3
/
4
).