ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 28
![no-image](/images/no-image-200.jpg)
ZL50050GAC
Manufacturer Part Number
ZL50050GAC
Description
8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50050GAC.pdf
(94 pages)
- Current page: 28 of 94
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SMPL_MODE = LOW
Please refer to Control Register (Section 14.1) for SMPL_MODE definition.
Figure 9 - Backplane and Local Input Bit Delay Timing Diagram for Data Rate of 16 Mbps
Bit Delay = 7 1/2
Bit Delay = 7 3/4
Bit Delay = 1/4
Bit Delay = 1/2
Bit Delay = 3/4
BSTi/LSTi0-15
BSTi/LSTi0-15
BSTi/LSTi0-15
BSTi/LSTi0-15
BSTi/LSTi0-15
BSTi/LSTi0-15
BSTi/LSTi0-15
Bit Delay = 0
Bit Delay = 1
(Default)
FP8i
C8i
3
Ch254
3
Ch254
3
Ch255
2
3
Ch255
2
Ch255
2
3
Ch255
2
Ch255
2
1
2
1
1
2
1
1
0
1
0
0
1
0
Zarlink Semiconductor Inc.
0
7
0
7
0
7
ZL50050
7
Bit Delay, 1/4
7
6
Bit Delay, 1/2
7
6
Bit Delay, 3/4
6
7
Bit Delay, 1
6
28
6
5
6
5
5
6
5
Ch255
5
Ch255
4
Ch0
5
4
4
Ch0
5
Ch0
4
Ch0
3
4
Ch0
3
4
3
4
3
3
2
3
2
2
3
2
2
1
2
1
1
2
1
1
0
1
0
0
1
0
0
7
0
Bit Delay, 7 1/2
7
7
0
Bit Delay, 7 3/4
7
7
6
7
6
6
7
6
6
Ch0
5
6
Ch0
5
Ch1
5
6
Ch1
5
Ch1
Ch1
5
4
Ch1
5
4
4
5
Data Sheet
4
4
4
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