ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 82

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ZL50050GAC

Manufacturer Part Number
ZL50050GAC
Description
8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
CK_int *
(244 ns)
(122 ns)
(244 ns)
(122 ns)
(122 ns)
Note *: CK_int is the internal clock signal of 131.072 MHz
Note **: Although the figures above show the frame boundary as measured from the falling edge of C8i/C8o/C16o, the
frame-controlling edge of C8i/C8o/C16o may be the rising edge, as configured via the C8iPOL and COPOL bits of the
Control Register.
FP16o
FP16o
(61ns)
FP8o
FP8o
C16o
FP8i
FP8i
C8o
C8i
Figure 24 - Input and Output Clock Timing Diagram for ST-BUS
t
OCL16
t
ICL
t
OCL8
t
t
IFPS244
OCH16
t
FPFBF8_244
t
FPFB16_61
t
IFPS122
t
t
FPFBF16_122
t
FPFBF8_122
ICH
t
OCH8
Zarlink Semiconductor Inc.
t
IFPW244
ZL50050
t
t
IFPW122
OFPW16_61
t
t
OFPW8_122
OFPW16_122
t
OFPW8_244
82
t
t
IFPH122
t
FBFPF16_122
OFBOS
t
FBFPF8_122
t
FBFP16_61
t
IFPH244
t
FBFPF8_244
t
ICP
t
OCP8
t
rOC16
t
rIC
t
rOC8
t
OCP16
t
fIC
t
t
fOC8
fOC16
Data Sheet

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