ZL50050GAC ZARLINK [Zarlink Semiconductor Inc], ZL50050GAC Datasheet - Page 77

• Manufacturer Part Number: ZL50050GAC
• Description: 8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.15
Address 3FFF
The Device Identification Register stores the binary value of the silicon revision number and the Device ID. This
register is read-only. The DIR register is configured as follows:
15:8
Bit
Bit
7:4
2:0
2
1
0
3
Device Identification Register
BISTSCL
BISTCCL
BISTPCL
Name
Reserved
Reserved
DID[2:0]
H
RC[3:0]
Name
.
Reset
Value
Table 54 - Memory BIST Register (MBISTR) Bits (continued)
0
0
0
Table 55 - Device Identification Register (DIR) Bits
Local Connection Memory Start BIST Sequence
Sequence enabled on LOW to HIGH transition.
Local Connection Memory BIST Sequence Completed (Read-only)
This bit must be polled - when HIGH, indicates completion of Local Connection
Memory BIST sequence.
Local Connection Memory Pass/Fail Bit (Read-only)
This bit indicates the Pass/Fail status following completion of the Local
Connection Memory BIST sequence (indicated by assertion of BISTCCL).
A HIGH indicates Pass, a LOW indicates Fail.
Reset Value
0000
010
0
0
Zarlink Semiconductor Inc.
ZL50050
Reserved
Will be set to 0 in normal operation
Revision Control Bits
Reserved
Will be set to 0 in normal operation
Device ID
77
Description
Description
Data Sheet