ZL50073GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50073GAG2 Datasheet

ZL50073GAG2

Manufacturer Part Number

ZL50073GAG2

Description

32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs

Manufacturer

ZARLINK [Zarlink Semiconductor Inc]

Datasheet

1.ZL50073GAG2.pdf (68 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

ZL50073GAG2

Manufacturer:

ZARLINK

Quantity:

500

Current page: 1 of 68
Download datasheet (617Kb)

Features

•

32,768 channel x 32,768 channel non-blocking

digital Time Division Multiplex (TDM) switch at

65.536 Mbps, 32.768 Mbps and 16.384 Mbps or

using a combination of rates

16,384 channel x 16,384 channel non-blocking

digital TDM switch at 8.192 Mbps

High jitter tolerance with multiple input clock

sources and frequencies

Up to 128 serial TDM input streams, divided into

32 groups with 4 input streams per group

Up to 128 serial TDM output streams, divided into

32 groups with 4 output streams per group

Per-group input and output data rate conversion

selection at 65.536 Mbps, 32.768 Mbps,

16.384 Mbps and 8.192 Mbps. Input and output

data group rates can differ

Per-group input bit delay for flexible sampling

point selection

Per-group output fractional bit advancement

Four sets of output timing signals for interfacing

additional devices

Per-channel A-Law/µ-Law Translation

CK_SEL1-0

CKo3-0

STiC31

STiD31

FPo3-0

STiA31

STiB31

CKi2-0

FPi2-0

STiC0

STiD0

STiA0

STiB0

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

VDD_CORE

Input

Timing

Converter

Timing

S/P

Figure 1 - ZL50073 Functional Block Diagram

VDD_IO

Microprocessor Interface

Zarlink Semiconductor Inc.

and Control Registers

VSS

32 K Channel Digital Switch with High Jitter

Connection Memory

Data Memory

Tolerance, Rate Conversion per Group of

•

Per-channel constant or variable throughput delay

for frame integrity and low latency applications

Per-stream Bit Error Rate (BER) test circuits

Per-channel high impedance output control

Per-channel force high output control

Per-channel message mode

Control interface compatible with Intel and

Motorola Selectable 32 bit and 16 bit non-

multiplexed buses

Connection Memory block programming

Supports ST-BUS and GCI-Bus standards for

input and output timing

IEEE 1149.1 (JTAG) test port

3.3 V I/O with 5 V tolerant inputs; 1.8 V core

voltage

4 Streams (8, 16, 32 or 64 Mbps),

ZL50073GAC

ZL50073GAG2

and 128 Inputs and 128 Outputs

Converter

P/S

**Pb Free Tin/Silver/Copper

Ordering Information

ODE

Output

Timing

Test Access

-40°C to +85°C

Port

484 Ball PBGA

484 Ball PBGA**

PWR

SToA0

SToB0

SToC0

SToD0

SToA31

SToB31

SToC31

SToD31

Data Sheet

Trays

ZL50073

January 2006

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