ZL50073GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50073GAG2 Datasheet - Page 52

• Manufacturer Part Number: ZL50073GAG2
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

14.7
The Block Init Register is a 32 bit read/write register at address 040288 - 04028B
The Block Init Register is used during block initialization of the connection memory. A block initialization
automatically occurs at power-up. However, it is possible to perform a block initialization at any time. During Block
Initialization, the value of the Block Init Register is copied to all connection memory locations in an operation that
runs in about 120 µs. If the Block Init Register is modified during a block initialization, the new value used is
ignored.
14.8
The Block Init Enable Register is a 32 bit read/write register at address 04028C - 04028F
The Block Init Enable Register is used to initiate a block initialization of the connection memory. A block initialization
automatically occurs at power-up. Since the Block Init Register is cleared at power-up this automatic block
initialization will write all zeros to all Connection Memory Bits. However, it is possible to perform a block initialization
at any time. To begin a block initialization, the hex value 31415926 must be written to the Block Init Enable Register.
If a block initialization is signaled while one is in progress, the signal is ignored, and the currently active block
initialization is allowed to complete.
The value read back from the Block Init Enable Register is different from the value written. It represents both the
block initialization status, and the power-up reset initialization status. The meaning of the initialization status bits is
illustrated in Table 28. The bits 31 - 2 always read back 0.
Any access to the connection memory or the data memory during a block initialization or a reset initialization will
result in a bus error, BERR. All TDM outputs are tri-stated during any block initialization.
Block Init Register
Block Init Enable Register
Bit
0
1
Reset Init Status
Block Init Status
Table 28 - Block and Power-up Initialization Status Bits
Name
Zarlink Semiconductor Inc.
ZL50073
1 if Reset initialization is in progress
1 if Block initialization is in progress
0 if Block initialization is completed;
0 if Reset initialization is completed
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Data Sheet