ZL50073GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50073GAG2 Datasheet - Page 18

• Manufacturer Part Number: ZL50073GAG2
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

2.0
The input timing for the ZL50073 can be set for one of four different frequencies. They can also be set for ST-BUS
or GCI-Bus mode with positive or negative input. The CKi0 and FPi0 input timing must be provided in order for the
device to be used. There are two additional input clocks and frame pulses that can be provided. CKi0 is used to
generate the internal clock. This clock is used for all the internal logic and can be used as one of the clocks that
defines the timing for the input and output data. The input stream clock source is selected by the ISSRC1 - 0 (bits 1
- 0) in the Group Control Registers. The output stream clock source is selected by the OSSRC1 - 0 (bits 17 - 16) in
the Group Control Registers.
The CKi0 and FPi0 input frequency is set via the CK_SEL1 - 0 pins as shown in Table 3. By default the CKi0 and
FPi0 pins accept ST-BUS, negative input timing. The input frame pulse format (ST-BUS/GCI-Bus), frame pulse
polarity, and clock polarity can be programmed by the GCISEL0 (bit 2), FPIPOL0 (bit 1), and CKIPSL0 (bit 0) in the
Input Clock Control Register (ICCR), as described in Section 14.5.
Two additional input clocks (CKi2 - 1) and frame pulses (FPi2 - 1) can be accepted. These signals can be
8.192 MHz, 16.384 MHz, 32.768 MHz or 65.536 MHz and the rates are automatically detected by the device.
These clocks and their frame boundaries must be phase aligned with the CKi0 and its frame boundary within a
30 ns skew but can have different jitter values. The clocks do not have to have the same frequency. If these
additional clocks are not used, the pins must be connected to a defined logic level.
Input Groups 0 - 23 at 65 Mbps; Output Groups 0 - 14 at 65 Mbps
Example:
Input Groups 24 - 27 at 32 Mbps; Output Groups 15 - 28 at 32 Mbps
Input Groups 28 - 31 at 16 Mbps; Output Groups 29 - 31 at 16 Mbps
Input Clock (CKi) and Input Frame Pulse (FPi) Timing
28 - 31 at 16 Mbps
24 - 27 at 32 Mbps
0 - 23 at 65 Mbps
Input Groups
Input Groups
Input Groups
Figure 4 - Input and Output Data Rate Conversion Example
CK_SEL1
STiC28 - 31 at 16 Mbps
STiD28 - 31 at 16 Mbps
STiA28 - 31 at 16 Mbps
STiB28 - 31 at 16 Mbps
STiA0 - 23 at 65 Mbps
STiA24 - 27 at 32 Mbps
STiB24 - 27 at 32 Mbps
STiC0 - 23 Not Active
STiB0 - 23 Not Active
STiD0 - 23 Not Active
STiC24 - 27 Not Active
STiD24 - 27 Not Active
Table 3 - CKi0 and FPi0 Setting via CK_SEL1 - 0
0
0
1
1
Zarlink Semiconductor Inc.
CK_SEL0
ZL50073
0
1
0
1
18
32K x 32K
Input CKi0 and FPi0
SToC29 - 31 at 16 Mbps
SToD29 - 31 at 16 Mbps
SToA15 - 28 at 32 Mbps
SToB15 - 28 at 32 Mbps
SToA29 - 31 at 16 Mbps
SToB29 - 31 at 16 Mbps
SToA0 - 14 at 65 Mbps
SToC15 - 28 Not Active
SToD15 - 28 Not Active
SToC0 - 14 Not Active
16.384 MHz
32.768 MHz
65.536 MHz
SToB0 - 14 Not Active
SToD0 - 14 Not Active
8.192 MHz
15 - 28 at 32 Mbps
0 - 14 at 65 Mbps
Output Groups
29 - 31 at 16 Mbps
Output Groups
Output Groups
Data Sheet