ZL50073GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50073GAG2 Datasheet - Page 12

• Manufacturer Part Number: ZL50073GAG2
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
A8, C9, B8, E10, A7, A6, D9,
B10, C10, A9, D10, B9, F11,
E9, C8, A5, B6, C7, D8, E8,
A4, B5, C6, D7, F8, A3, B4
D13, B15, A15, B14, C13,
B16, A17, A16, C14, E13,
A14, B13, E12, D12, A13,
A11, C11, E11, B11, A10,
A18, J21, M22, R3, V13,
W13, Y13, AA16, AA17
C12, D11, B12, A12
A1, AB4, R18, E14
G5, Y6, T19, C17
AB13, AB14
W15, V14
Pin
L1
CK_SEL0-1
CKo0-3
FPo0-3
Name
D0-31
A0-18
ODE
NC
IC
Microprocessor Port and Reset
Zarlink Semiconductor Inc.
ST-BUS/GCI-Bus Clock Outputs (3.3 V Outputs with Slew-Rate
Control)
These clock outputs can be programmed to generate 8.192 MHz,
16.384 MHz, 32.678 MHz or 65.536 MHz TDM clock outputs. The
active edge can be programmed to be either rising or falling. The
source of the clock outputs can be derived from either the CKi2-0
inputs or the internal system clock. The frequency, active edge and
source of each clock output can be programmed independently by
the Output Clock Control Register (Section 14.6). For 65.536 MHz
output clock, the total loading on the output should not be
larger than 10pF
ST-BUS/GCI-Bus Frame Pulse Outputs (3.3 V Outputs with
Slew-Rate Control)
These 8 kHz output pulses mark the frame boundary of the TDM
data streams. The pulse width is nominally one clock period of the
corresponding CKo output. The active state of each frame pulse
may be either high or low, independently programmed by the
Output Clock Control Register (Section 14.6).
Master Clock Input Select (5 V Tolerant Inputs)
Inputs used to select the frequency and frame alignment of CKi0
and FPi0:
CK_SEL1 = 0, CK_SEL0 = 0, 8.192 MHz
CK_SEL1 = 0, CK_SEL0 = 1, 16.384 MHz
CK_SEL1 = 1, CK_SEL0 = 0, 32.768 MHz
CK_SEL1 = 1, CK_SEL0 = 1, 65.536 MHz
Output Drive Enable (5 V Tolerant Input with Internal Pull-up)
This is the asynchronous output enable control for the output
streams. When it is high, the streams are enabled. When it is low,
the output streams are tristated.
Internal Connections
In normal mode these pins MUST be connected low
No Connection
In normal mode these pins MUST be left unconnected
Microprocessor Port Data Bus (5 V Tolerant Bi-directional with
Slew-Rate Output Control)
32 or 16 bit bidirectional data bus. Used for microprocessor access
to internal memories and registers. When 16 bit mode is selected
(D16B is logic 1), D31-16 are unused and must be connected to
defined logic levels.
Microprocessor Port Address Bus (5 V Tolerant Inputs)
19 bit address bus for the internal memories and registers. In 16 bit
bus mode (D16B is logic 1), please note A0 is not used and must
be connected to a defined logic level.
In Intel 32 bit mode: A1 = BE
ZL50073
12
.
Description
3
, A0 = BE
2
Data Sheet