ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 27

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.2
All PAC Interface signals are 5 V tolerant
All PAC Interface outputs are high impedance while System Reset is LOW.
TDM_CLKiP
TDM_CLKiS
PLL_PRI
PLL_SEC
PAC Interface
Signal
I/O
OT
OT
I D
I D
C1
D3
U1
V1
Table 6 - PAC Interface Package Ball Definition
Package Balls
Zarlink Semiconductor Inc.
ZL50110/11/14
27
Primary reference clock input. Should be
driven by external clock source to provide
locking reference to internal / optional
external DPLL in TDM master mode. Also
provides PRS clock for RTP timestamps in
synchronous modes.
Acceptable frequency range: 8 kHz -
34.368 MHz.
Secondary reference clock input. Backup
external reference for automatic switch-over
in case of failure of TDM_CLKiP source.
Primary reference output to optional
external DPLL.
Multiplexed & frequency divided reference
output for support of optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
Secondary reference output to optional
external DPLL Multiplexed & frequency
divided reference output for support of
optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
Description
Data Sheet