ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 52

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

5.3.3
The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for
unstructured TDM data. The ZL50110/11/14 is capable of providing the TDM clock for either of the modes. The
ZL50110/11/14 supports clock recovery in both synchronous and asynchronous modes of operation. In
asynchronous operation each stream may have independent clock recovery.
5.3.3.1
In synchronous mode all 32 streams will be driven by a common clock source. When the ZL50110/11/14 is acting
as a master device, the source can either be the internal DPLL or an external PLL. In both cases, the primary and
secondary reference clocks are taken from either two TDM input clocks, or two external clock sources driven to the
chip. The input clocks are then divided down where necessary and sent either to the internal DPLL or to the output
pins for connection to an external DPLL. The DPLL then provides the common clock and frame pulse required to
drive the TDM streams. See “DPLL Specification” on page 66 for further details.
When the ZL50110/11/14 is acting as a slave device, the common clock and frame pulse signals are taken from an
external device providing the TDM master function.
5.3.3.2
Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be
controlled to recover the clock from the original TDM source depending on the timing algorithm used.
5.4
Data traffic received on the TDM Access Interface is sampled in the TDM Interface block, and synchronized to the
internal clock. It is then forwarded to the payload assembly process. The ZL50110/11/14 Payload Assembler can
handle up to 128 active packet streams or “contexts” simultaneously. Packet payloads are assembled in the format
shown in Figure 14 on page 54. This meets the requirements of the CESoPSN standard under development in the
IETF. Alternatively, packet payloads are assembled in the format shown in Figure 16 on page 56. This meets the
requirements of the SAToP standard under development in the IETF
When the payload has been assembled it is written into the centrally managed memory, and a task message is
passed to the Task Manager.
Payload Assembly
TDM Clock Structure
TDM_CLKi[31:0]
Synchronous TDM Clock Generation
Asynchronous TDM Clock Generation
TDM_CLKiP
TDM_CLKiS
Figure 13 - Synchronous TDM Clock Generation
PRS
SRS
Zarlink Semiconductor Inc.
ZL50110/11/14
52
PRD
SRD
DIV
DIV
Internal
DPLL
CLOCK
FRAME
PLL_PRI
PLL_SE
C
Data Sheet