ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 91

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

11.10
Note 1:
Note 2:
Note 3:
JTAG_CLK period
JTAG_CLK clock pulse width
JTAG_CLK rise and fall time
JTAG_TRST setup time
JTAG_TRST assert time
Input data setup time
Input Data hold time
JTAG_CLK to Output data valid
JTAG_CLK to Output data high
impedance
JTAG_TMS, JTAG_TDI setup time
JTAG_TMS, JTAG_TDI hold time
JTAG_TDO delay
JTAG_TDO delay to high
impedance
JTAG_TRST is an asynchronous signal. The setup time is for test purposes only.
Non Test (other than JTAG_TDI and JTAG_TMS) signal input timing with respect to JTAG_CLK.
Non Test (other than JTAG_TDO) signal output with respect to JTAG_CLK.
JTAG Interface Timing
Parameter
Symbol
Table 41 - JTAG Interface Timing
t
t
RSTSU
TOPDV
t
t
t
t
t
TPSU
t
t
t
LOW,
HIGH
t
t
RST
TPH
JCP
JRF
JSU
t
JDV
TPZ
t
JH
JZ
Zarlink Semiconductor Inc.
ZL50110/11/14
Min.
40
20
10
10
15
15
0
5
0
0
5
0
0
91
Typ.
100
-
-
-
-
-
-
-
-
-
-
-
-
Max.
20
20
15
15
3
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
With respect to
JTAG_CLK
falling edge.
Note 1
Note 2
Note 2
Note 3
Note 3
Data Sheet
Notes