ZL50114GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50114GAG2 Datasheet - Page 40

• Manufacturer Part Number: ZL50114GAG2
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

CPU_OE
CPU_TS_ALE
CPU_SDACK1
CPU_SDACK2
CPU_CLK
CPU_TA
Signal
Table 14 - CPU Interface Package Ball Definition (continued)
I/O
OT
I
I
I
I
I
AE14
AE15
AF15
AD15
AC14
AB14
Package Balls
Zarlink Semiconductor Inc.
ZL50110/11/14
40
CPU Output Enable.
Synchronous input with rising edge of
CPU PowerQUICC™ II Bus Interface
Synchronously asserted with respect to
CPU_CLK rising edge, and active low.
Used for CPU reads from the processor
to registers within the ZL50110/11/14.
Asserted one clock cycle after
CPU_TS_ALE. Must be asserted with
CPU_CS to asynchronously enable the
CPU_DATA output during a read,
including DMA read.
CPU_CLK.
Latch Enable (ALE), active high signal.
Asserted with CPU_CS, for a single
clock cycle.
CPU/DMA 1 Acknowledge Input. Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL50110/11/14 for a DMA write
transaction. Only used for DMA
transfers, not for normal register access.
CPU/DMA 2 Acknowledge Input Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL50110/11/14 for a DMA read
transaction. Only used for DMA
transfers, not for normal register access.
clock input. 66 MHz clock, with minimum
of 6 ns high/low time. Used to time all
host interface signals into and out of
ZL50110/11/14 device.
CPU Transfer Acknowledge. Driven from
tri-state condition on the negative clock
edge of CPU_CLK following the
assertion of CPU_CS. Active low,
asserted from the rising edge of
CPU_CLK. For a read, asserted when
valid data is available at CPU_DATA.
The data is then read by the host on the
following rising edge of CPU_CLK. For a
write, is asserted when the
ZL50110/11/14 is ready to accept data
from the host. The data is written on the
rising edge of CPU_CLK following the
assertion. Returns to tri-state from the
negative clock edge of CPU_CLK
following the de-assertion of CPU_CS.
Description
Data Sheet